集成电路中多晶硅薄膜载流子迁移率的实验研究和理论模型

本文系统地研究了多晶硅薄膜载流子迁移率与掺杂浓度的关系,发现不仅如前人所指出的那样,多晶硅载流子迁移率在中等掺杂区有一极小值,而且同时在高掺杂区存在一个极大值.本文将前人提出的杂质分凝模型、晶粒间界陷阱模型和杂质散射机构结合起来,从理论上计算了极大值及其相应的掺杂浓度与晶粒大小、晶粒间界界面态密度的关系,并与实验结果进行了比较.理论模型较好地说明了实验结果.     

铝原子晶粒间界分凝及其对多晶硅电学特性的影响

本文用俄歇电子能谱(AES)证明了铝原子在多晶硅晶粒间界分凝的现象,并研究了多晶硅的势垒电阻、少子寿命和霍耳迁移率.实验结果表明:铝原子的晶粒间界分提与铝原子的性质、铝原子扩散温度以及多晶硅的结构有关;铝原子晶粒间界分凝能在一定程度上改善多晶硅的电学特性,显示出铝原子晶粒间界分凝具有一定的应用潜力.     

多晶硅太阳电池的一维模拟计算

提出了多晶硅太阳电池的一维物理模型,并对其在AM1.5太阳光照下的电池的短路电流密度Jsc、开路电压Voc、填充因子FF和转换效率η进行了模拟计算,重点分析了多晶硅晶粒尺寸和电池厚度对n /p结构的多晶硅太阳电池性能的影响.模拟中主要引入载流子的有效迁移率和有效扩散长度两个物理量.模拟结果表明,电池效率在厚度50μm以内随厚度的增加而增大,当厚度大于50μm以后趋于饱和;当晶粒尺寸在100 μm以内时,电池特性随晶粒尺寸的增加而显著提高,晶粒进一步增大时效率趋于饱和,此时背面复合速率的影响变大.     

扩硼多晶硅层的电学特性

应用Van der pauw法测试了扩硼多晶硅层的电阻率、载流子浓度和霍尔迁移率,对多晶硅层的厚度、淀积、温度以及硼扩散的温度和时间对这些电学特性的影响进行了研究。发现合乎硅栅MOS器件要求的硼扩散条件是950℃半小时。在此条件下测得电阻率是1.2×10~(-3)Ωcm。当多晶硅层的厚度和淀积温度增加时,由于颗粒变大,霍尔迁移率也随着增大,在本实验范围内,测得霍尔迁移率的最大值是30厘米~2/伏·秒。对硼扩散与载流子浓度的关系用多晶硅——氧化物——单晶硅结构的简化模型进行了分析。发现载流子浓度是随着一个无量纲的变量1/L_P(=D_P~t/l_y~2)的增加而增加,并且由于硼在晶粒间界的沉淀而出现饱和,饱和时的载流子浓度大约是硼在单晶硅衬底中最大固溶度的百分之四十。     

激光改善太阳能材料电学特性的研究

在制备多晶硅太阳能电池材料的过程中,离子注入和机械加工往往使材料表层微结构产生缺陷,恶化了材料的电学性能,降低了少数载流子寿命。针对这一问题,本实验采用高功率CO2激光扫描硅材料,通过晶粒外延生长消除了缺陷,降低了材料表面方块电阻,提高了少数载流子寿命。本文还分析了激光扫描后材料的反型现象。     

激光区熔再结晶SOI的杂质分布与迁移率研究

本文介绍一种确定ＳＯＩ／ＭＯＳ结构中沿硅薄膜厚度多子漂移分布和杂质分布的简单方法（其掺杂剖面是随机不均匀的）。这种方法基于使用一种耗尽型晶体管与栅控二极管的组合结构。作者列举在激光区熔再结晶多晶硅制的ＳＯＩ结构和ＳＯＳ结构上以相同工艺制作器件的对比研究结果。由这些结果可见，在包含有晶粒间界和子晶粒间界的ＳＯＩ薄膜中，沿膜厚的载流子迁移率是恒定的，而且远远超过ＳＯＳ膜中的迁移率。     

高频光电导衰减法测试Ge单晶少数载流子寿命

高频光电导衰减法是测量Ge单晶少数载流子寿命常用的方法,高频脉冲信号照射到单晶表面时,产生非平衡载流子,非平衡载流子的复合时间长短反映了少数载流子寿命的大小。电阻率越低,少数载流子寿命越小,仪器就难以测试。介绍了电阻率为0.03~0.04Ω.cm Ge单晶少数载流子寿命的测试方法。通过理论分析及实际测试,发现影响Ge单晶测试的主要因素有3个,即样品的表面状态、厚度及测试仪器的小注入水平。通过规范这些测试条件,能够测试低阻Ge单晶的少数载流子寿命。     

低温多晶硅发射极晶体管电流增益和截止频率的解析模型

本文综合考虑了多晶硅发射极的载流子输运障碍,界面氧化物遂穿、晶粒间界杂质分凝和界面能带弯曲等因素,以及禁带变窄效应、低温下载流子冻析效应和浅能能补偿杂质隐阱效应,建立了低温多晶硅发射极晶体管电流增益和截止频率的解析模型,对电流增益和截止频率的温度关系进行了理论分析并与３００Ｋ和７７Ｋ下的实测结果进行了比较。     

太阳能电池光载流子辐射复合的红外特性仿真与试验

激光诱发硅太阳能电池产生载流子,由于少数载流子的复合而发射红外辐射.基于一维载流子传输方程,建立了调制激光诱发PN结少数载流子密度模型,利用该模型仿真分析了载流子寿命、扩散率、表面复合率及光电压对辐射复合产生红外辐射信号的影响.利用InGaAs红外探测器(0.9~1.7μm)记录激光诱发载流子辐射复合的红外辐射信号,用数字锁相放大器提取了幅值与相位.通过频率扫描试验获得了多晶硅太阳能电池载流子传输参数.     

InGaAsP发光二极管的电流-功率特征中俄歇复合占优势

在以往的文章中,一些作者认为俄歇复合可能是InGaAsP发光二极管(LED)输出功率饱和的机理。然而,最近一些报道则认为功率饱和也可能是由裁流子受热和载流予泄漏的影响。本文提出进一步的实验结果,强有力地证明俄歇复合是功率饱和的主要原因。对于各种有源层厚度(d=0.2～2μm)1.3μm的InGaAsP LED,测量了电流一功率关系和载流子寿命。在恒定注入栽流子密度     

Current gain in polysilicon emitter transistors

The common-emitter current gain β in a shallow polysilicon emitter transistor is derived by solving the minority-carrier transport equation in the silicon-polysilicon structure. Coupled With the majority-carrier transport, an equation for the current gain is obtained which depends on the physical properties of the polysilicon as well as the silicon emitter and base doping profiles. The calculations are based on the carrier trapping model proposed in the literature and ignore any minority-carrier recombinations. The model predicts the current gain of a polysilicon emitter transistor increases at low current and high temperature and approaches that of a conventional metal contact transistor at high current and low temperature. This is due to the potential barrier across the grain boundaries, while impeding the majority-carrier flow, inject minority carriers as a bias is developed across the grain boundaries. It also predicts a decrease in cutoff frequency fTdue to minority carriers stored in the polysilicon.     

A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors

A comprehensive model-both analytical and numerical-is proposed as a tool to analyze heavily doped emitters of transistors with polycrystalline silicon (polysilicon) contacts. The grains and grain boundaries of polysilicon, the interfacial oxide-like layer between polycrystalline and monocrystalline silicon are lumped respectively into "boxes" in which the drift minority current component is neglected. The mobility reduction of carriers in polysilicon on the whole is explicitly attributed to the additional scattering due to the lattice disorder in the grain boundaries and the carrier tunneling through the interface. The effect of the poly-contacts on transistors can be modeled as a reduced surface recombination velocity for minority carriers in combination with a series emitter resistance for majority carriers. Furthermore, by characterizing the monocrystalline emitter with an effective recombination velocity, the effect of the polysilicon layer on the current gain can be analyzed analytically. Computer simulation is used to verify the assumptions of the model formulation. Using published data [1], the analytical and numerical approaches are compared and it is shown that for these devices a unique combination of physical parameters are needed for the model to fit the data.     

On-state drain current modeling of large-grain poly-Si TFTs based on carrier transport through latitudinal and longitudinal grain boundaries

An analytical on-state drain current model of large-grain polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented, based on the carrier transport through latitudinal and longitudinal grain boundaries. The model considers an array of square grains in the channel, with the current flowing along the longitudinal grain boundaries or through the grains and across the latitudinal grain boundaries. Application of the proposed model to excimer lased annealed polysilicon TFTs reveals that, at low gate voltages in the moderate inversion region, the longitudinal grain boundaries influence the effective carrier mobility and the drain current. As the gate voltage increases, the latitudinal grain boundaries have larger impact to the current flow due to reduction of the potential barrier at the grain boundaries. The effect of the laser energy density on the quality of the grains and grain boundaries is investigated.     

The effect of grain boundary shunt currents on mis solar cell performance

The degradation of solar cells by grain boundaries can take any of three forms: recombination of minority carriers, forward current due to recombination in the space charge region of the junction or Schottky barrier, or forward currents due to shunting. There is no doubt that minority carrier recombination occurs and degrades the short circuit current. There seems little doubt that grain boundaries also degrade the solar cell open circuit voltage, but whether the degradation is due to recombination in the space charge region or due to shunting is not clear. To date most attention has been paid to space charge recombination. There is data, however, that shunt currents can flow, especially in doped regions of the grain boundaries with the conductivity along the grain boundary estimated from that data to be 10⁻¹² to 10⁻⁵ mhos/square. We will present an analysis assuming such grain boundary conductivities and show that the predictions of such a shunt model are in agreement with experiment. Specifically the shunt current is predicted to increase exponentially as qV/2kT where V is the forward bias, the shunt current significantly lowers the open circuit voltage, and it has negligible effect on the short circuit current.     

集成电路中金属连线下多晶硅电阻的不稳定性分析及抑制方法

作为集成电路的电阻单元,掺硼的多晶硅电阻在千欧级的范围内存在阻值不稳定性,尤其在金属连线下更为严重．分析了不同工艺条件下制作的多晶硅电阻电特性和晶格特性．结果表明,阻值的不稳定性主要由载流子迁移率改变引起．通过测试和运用Seto’s模型计算进一步发现,在铝连线底下势垒高度和俘获的电荷密度均有降低．电荷的俘获／反俘获在多晶硅晶粒边界发生引起势垒高度的变化,从而导致阻值不稳定．然后,借助于补偿的离子注入制作了高稳定的、阻值在千欧级的多晶硅电阻．该方法使得多晶硅晶粒边界电荷的俘获／反俘获对氢退火不敏感．     

Recombination velocity at grain boundaries in polycrystalline Si under optical illumination

Calculations have been performed of recombination currents at grain boundaries in polycrystalline silicon for three different energy distributions of recombination centers. These results show that the relationship between the recombination current density and the minority carrier concentration at the grain boundary, under conditions of optically induced separation of the electron and hole quasi-Fermi levels, is highly nonlinear. It is further shown that the recombination velocity is an increasing function of the minority carrier concentration at the grain boundary. In this calculation, it is necessary to relax the earlier assumptions [1] of equal capture cross sections for electrons and holes of the grain boundary recombination centers and [2] of a flat minority-carrier quasi-Fermi level in the space-charge region, since these assumptions prove to be unjustified in the general case.     

Physical Model for the Resistivity and Temperature Coefficient of Resistivity in Heavily Doped Polysilicon

One of the key benefits of using polysilicon as the material for resistors and piezoresistors is that the temperature coefficient of resistivity (TCR) can be tailored to be negative, zero, or positive by adjusting the doping concentration. This paper focuses on optimization of the boron doping of low-pressure chemical vapor deposited polysilicon resistors for obtaining near-zero TCR and development of a physical model that explains quantitatively all the results obtained in the optimization experiments encompassing the doping concentration ranges that show negative, near-zero, and positive TCR values in the polysilicon resistors. The proposed model considers single-crystal silicon grain in equilibrium with amorphous silicon grain boundary. The grain boundary carrier concentration is calculated considering exponential band tails in the density of states for amorphous silicon in the grain boundaries. Comparison of the results from the model shows excellent agreement with the measured values of resistivity as well as TCR for heavily doped polysilicon. It is shown that the trap density for holes in the grain boundary increases as the square root of the doping concentration, which is consistent with the defect compensation model of doping in the amorphous silicon grain boundaries.     

A large-bias conduction model of polycrystalline silicon films

There exists a need for a large-bias conduction model of polysilicon films used in VLSI/ULSI and in high power integrated circuits. A large-bias conduction model has been developed by extending the emission-based models of Lu et al. (1983) and Mandurah et al. (1981) valid for small-bias, small-signal conditions. The following large-bias effects have been taken into account: (1) asymmetry of potential distribution around grain boundaries and (2) avalanche multiplication of carriers in the grain boundary layers at high electric fields. Since the exact nature of the grain boundary material is not yet known, and there is no direct method for determining the model parameters relating to grain boundaries, these were extracted by the parametric fitting of resistance versus temperature data of polysilicon resistors near room temperature with the above small-signal resistivity models modified by including Fermi-Dirac distribution. The model has been validated with experimental data on the current-voltage characteristics of ion-beam sputtered polysilicon resistors of different sizes and aspect ratios. The dependence of model parameters relating to grain boundary scattering and avalanche multiplication on the dimensions of resistors have been explained physically. The increased kink effect in polysilicon TFT's may also be predicted from the present theory. Some results on the I-V characteristics of polyresistors trimmed by high current pulses have been discussed qualitatively in the light of the present model. Although the model involves numerical integrations and a few iterations, it is reasonably fast in execution     

Electrical trimming of ion-beam-sputtered polysilicon resistors byhigh current pulses

Phosphorus doped polysilicon resistors have been fabricated from microcrystalline silicon films which were deposited by ion beam sputtering using an argon ion beam of diameter 3 cm, energy 1 keV and current density 7mA/cm², with a deposition rate of 100-120 Å/min. The resistors, having a sheet resistance of 70 Ω/square and a carrier concentration of 7.5×10¹⁹ cm^-3, were stressed with current pulses of width 10 μs and duty cycle 0.6% for 5 min. There was a steady decrease of resistance with increasing pulse current density above a threshold value 5×10 ⁵ A/cm². A maximum fall of 27% was observed for a 95 μm long resistor. The current-voltage characteristics were also recorded during the trimming process. The trimming characteristics were simulated using a small-signal resistivity model of Lu et al. (1983). and the I-V characteristics by a large-bias conduction model. A close fitting of the experimental data with the theoretical values needed an adjustment of some grain boundary parameters for the different pulse current densities used for stressing. The nature of variation of the grain boundary parameters indicates that the rapid Joule heating of the grain boundaries due to current pulses passivates the grain boundary interfaces, at lower currents above the threshold, and then, at higher values of currents, causes zone melting and gradual recrystallization of the disordered boundary layers and subsequent dopant segregation. It confirms the mechanism suggested in the physical model of Kato et al. (1982). The role played by the field-enhanced diffusivity and electromigration of dopant ions, due to the high instantaneous temperature of the grain boundaries, has also been discussed. The pulse trimming technique is simple and does not cause damage to the adjacent components on a monolithic chip     

The effects of grain boundary and interface recombination on the performance of thin-film solar cells

The effects of grain boundary and interface minority carrier recombination on polycrystalline thin-film photovoltaic heterojunctions are presented. The grain boundary is modeled accounting for interface states, due to low-, medium- and high-angle grain boundaries. The dark and illuminated diffusion potentials are calculated as functions of interface state densities and carrier concentrations. These are used to estimate the recombination velocities and minority carrier lifetimes. These parameters are, in turn, correlated with the short-circuit currents and open-circuit voltages. The dependence of V_oc upon grain diameter is predicted. Junction interface states are discussed in terms of a dislocation model. The dependence of V_oc, affected primarily through dark reverse current, on the recombination velocity is indicated. The combined effects of grain boundary and interface recombination mechanisms on J_sc is discussed. Data are presented to verify the model based upon the CdS/CuInSe₂ photovoltaic heterojunction.