Effect of band alignment and density of states on the collector current in p-Si/n-Si/sub 1-y/C/sub y//p-Si HBTs

p-Si/n-Si/sub 1-y/C/sub y//p-Si heterojunction bipolar transistors with varying carbon fractions in the base were grown by rapid thermal chemical vapor deposition (RTCVD), to better understand the potential of Si/sub 1-y/C/sub y/ in enhancing the performance of Si-based bipolar technology. The band line-up issues which make Si/sub 1-y/C/sub y/ a desirable choice for forming the base region in a p-n-p HBT are discussed. Electrical measurements performed on the p-Si/n-Si/sub 1-y/C/sub y//p-Si HBTs (y=0.6, 0.8 at.%) are used to extract important information regarding the electronic properties of the Si/Si/sub 1-y/C/sub y/ material system, e.g., the bandgap reduction in Si/sub 1-y/C/sub y/ compared to Si and minority carrier recombination lifetime in Si/sub 1-y/C/sub y/. Temperature dependent measurements of the collector current were performed to extract the bandgap narrowing at the Si/Si/sub 1-y/C/sub y/ heterojunction. This paper includes a detailed analysis of the impact of heavy doping and reduced density of states in Si/sub 1-y/C/sub y/ compared to Si on the extraction of the energy bandgap offset, and on the collector current of p-n-p HBTs. The impact of the reduced density of states on the design of p-n-p Si/Si/sub 1-y/C/sub y/ HBTs is discussed. The measured value of the energy band offset is (65 meV/at.% C) very close to previously measured values of the conduction band offset at the Si/Si/sub 1-y/C/sub y/ heterojunction. The results are thus consistent with a band line-up at the Si/Si/sub 1-y/C/sub y/ interface that is dominated by a conduction band offset with little if any valence band offset.     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

MOS capacitors on epitaxial Ge-Si/sub 1-x/Ge/sub x/ with high-/spl kappa/ dielectrics using RPCVD

We report the successful growth of MOS capacitor stacks with low temperature strained epitaxial Ge or Si/sub 1-x/Ge/sub x/(x=0.9) layer directly on Si substrates, and with HfO/sub 2/(EOT=9.7 /spl Aring/) as high-/spl kappa/ dielectrics, both using a novel remote plasma-assisted chemical vapor deposition technique. These novel MOS capacitors, which were fabricated entirely at or below 400/spl deg/C, exhibit normal capacitance-voltage and current-voltage characteristics.     

A super self-aligned selectively grown SiGe base (SSSB) bipolartransistor fabricated by cold-wall type UHV/CVD technology

A novel selective epitaxial growth (SEG) technology for fabricating the intrinsic SiGe-base layer of a double poly-Si self-aligned bipolar transistor has been developed. Selectively grown Si and SiGe-alloy layers were obtained by using Si₂H₆+GeH₄+Cl₂+B₂ H₆ gas system using cold-wall ultra-high vacuum (UHV)/CVD. We have optimized the growth conditions so that Si or SiGe grows selectively against Si₃N₄ both on single crystalline Si and on poly-Si of a structure consisting of a poly-Si layer overhanging the single crystalline Si substrate. The selective growth is maintained until the growth from the bottom Si and the top poly-Si coalesce. This selective growth permits a novel emitter-base self-aligned transistor which we call a super self-aligned selectively grown SiGe base (SSSB) HBT     

High frequency performance of Si/sub 1-x/Ge/sub x//Si/sub 1-y/Ge/sub y//Si/sub 1-x/Ge/sub x/ HBTs

The results of a theoretical study of the performance of high speed SiGe HBTs is presented. The study includes a group of SiGe HBTs in which the Ge concentration in the base is 20% higher than that in the emitter and collector (i.e. y=x+0.2). It is shown that the composition dependences of f/sub T/ and the F/sub max/ are non-monotonic. As the Ge composition in the emitter and collector layers is increased, f/sub T/ and f/sub max/ first decrease, then remain constant and finally increase to attain their highest values.<>     

A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.     

Light emission near 1.3 /spl mu/m using ITO-Al/sub 2/O/sub 3/-Si/sub 0.3/Ge/sub 0.7/-Si tunnel diodes

We have fabricated Sn : In/sub 2/O/sub 3/ (ITO)-Al/sub 2/O/sub 3/ dielectric on Si/sub 1-x/Ge/sub x/-Si metal-oxide-semiconductor tunnel diodes which emit light at around 1.3 /spl mu/m, for x=0.7. The emitted photon energy is smaller than the bandgap energy of Si, thus, avoiding strong light absorption by the Si substrate. The optical device structure is compatible with that of a metal-oxide-semiconductor field-effect transistor, since a conventional doped poly-Si gate electrode will be transparent to the emitted light. Increasing the Ge composition from 0.3 to 0.4 only slightly decreases the light-emitting efficiency.     

High-speed scaled-down self-aligned SEG SiGe HBTs

A scaled-down self-aligned selective-epitaxial-growth (SEG) SiGe HBT, structurally optimized for an emitter scaled down toward 100 nm, was developed. This SiGe HBT features a funnel-shaped emitter electrode and a narrow separation between the emitter and base electrodes. The first feature is effective for suppressing the increase of the emitter resistance, while the second one reduces the base resistance of the scaled-down emitter. The good current-voltage performance - a current gain of 500 for the SiGe HBT with an emitter area of 0.11 /spl times/ 0.34 /spl mu/m and V/sub BE/ standard deviation of less than 0.8 mV for emitter width down to about 0.13 /spl mu/m - demonstrates the applicability of this SiGe HBT with a narrow emitter. This SiGe HBT demonstrated high-speed operation: an emitter-coupled logic (ECL) gate delay of 4.8 ps and a maximum operating frequency of 81 GHz for a static frequency divider.     

Effect of the composition on the electrical properties of TaSi/sub x/N/sub y/ metal gate electrodes

In this letter, the effect of silicon and nitrogen on the electrical properties of TaSi/sub x/N/sub y/ gate electrode were investigated. The TaSi/sub x/N/sub y/ films were deposited on SiO/sub 2/ using reactive cosputtering of Ta and Si target in Ar and N/sub 2/ ambient. The thermal stability of TaSi/sub x/N/sub y//SiO/sub 2//p-type Si stacks was evaluated by measuring the flatband voltage and equivalent oxide thickness at 400/spl deg/C and 900/spl deg/C in Ar. It was found that under high temperature anneals, Si-rich TaSi/sub x/N/sub y/ films increased and this was attributed to the formation of a reaction layer at the electrode-dielectric interface. Reducing the Si content alone did not prevent the formation of this reaction layer while removing Si completely by utilizing TaN resulted in work functions that were too high. The presence of both Si and N was deemed necessary and their content was critical in obtaining optimized TaSi/sub x/N/sub y/ gates that are suitable for NMOS devices.     

Waveguided electro-optical intensity modulation in a Si/Ge/sub x/Si/sub 1-x//Si heterojunction bipolar transistor

Optical phase-and-amplitude modulation at 1.55 mu m in an electro-optic guided-wave Si/Ge/sub 0.2/Si/sub 0.8//Si HBT is investigated using computer-aided modelling and simulation. At an injection of 10/sup 19/ electrons per cm/sup 3/, an intensity modulation of 10 dB is predicted for an active length of 390 mu m.<>     

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si/sub 1-x/Ge/sub x/ S/D) technology. Experimental results on Si/sub 1-x/Ge/sub x/ S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si/sub 1-x/Ge/sub x/ is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si/sub 1-x/Ge/sub x/ and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si/sub 1-x/Ge/sub x/ S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes.     

Mobility enhancement in surface channel SiGe PMOSFETs with HfO/sub 2/ gate dielectrics

We report for the first time drive current enhancement and higher mobilities than the universal mobility for SiO/sub 2/ on Si in compressively strained Si/sub 1-x/Ge/sub x/-on-Si surface channel PMOSFETs with HfO/sub 2/ gate dielectrics, for gate lengths (L/sub G/) down to 180 nm. Thirty six percent drive current enhancement was achieved for Si/sub 0.8/Ge/sub 0.2/ channel PMOSFETs compared to Si PMOSFETs with HfO/sub 2/ gate dielectric. We demonstrate that using Si/sub 1-x/Ge/sub x/ in the channel may be one way to recover the mobility degradation due to the use of HfO/sub 2/ on Si.     

用离子注入和掩埋金属自对准技术改善Si/SiGe HBT性能

在器件纵向结构确定后,常规工艺制作的SiGe／SiHBT噪声性能不理想的主要原因是其基极电阻较大,高频性能不理想主要是由于其基极和发射极台面面积较大造成的;为达到改善其高频与低噪声性能的目的,在不改变光刻工艺精度的情况下,采用离子注入和掩埋金属自对准工艺方法完成了器件制作;与传统制作方法相比,前者可减小外基区电阻,后者可以减小电极接触电阻,并能使器件的台面面积做得更小。在此基础上,我们测试了器件的最小噪声系数与最高截止频率,结果表明：用自对准工艺制作的器件的高频噪声与频率性能都显著改善。     

Very-low-threshold, strained In/sub y/Ga/sub 1-y/As-GaAs quantum-well lasers defined by impurity-induced disordering

Strained In/sub y/Ga/sub 1-y/As-GaAs quantum-well (InGaAs-QW) stripe geometry lasers ( lambda approximately 9050 AA) were fabricated by impurity-induced disordering (IID) through self-aligned Si-Zn diffusion. Lasers exhibit very low threshold (I/sub th/=3.0 mA at room-temperature continuous operation) and good uniformity (>90% with I/sub th/<8 mA, >70% with I/sub th/=4+or-1 mA). The moderate blue shift of the lasing wavelength (250 A or 40 meV) suggests that the strained InGaAs-QW active layer can survive long-time high-temperature thermal annealing (850 degrees C, 8 h) required for Si diffusion.<>     

Over 300 GHz f/sub T/ and f/sub max/ InP/InGaAs double heterojunction bipolar transistors with a thin pseudomorphic base

Describes 150-nm-thick collector InP-based double heterojunction bipolar transistors with two types of thin pseudomorphic bases for achieving high f/sub T/ and f/sub max/. The collector current blocking is suppressed by the compositionally step-graded collector structure even at J/sub C/ of over 1000 kA/cm/sup 2/ with practical breakdown characteristics. An HBT with a 20-nm-thick base achieves a record f/sub T/ of 351 GHz at high J/sub C/ of 667 kA/cm/sup 2/, and a 30-nm-base HBT achieves a high value of 329 GHz for both f/sub T/ and f/sub max/. An equivalent circuit analysis suggests that the extremely small carrier-transit-delay contributes to the ultrahigh f/sub T/.     

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.     

SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems

Technologies for a self-aligned SiGe heterojunction bipolar transistor (HBT) and SiGe HBTs with CMOS transistors (SiGe BiCMOS) have been developed for use in optical transmission and wireless communication systems. n-Si cap/SiGe-base multilayer fabricated by selective epitaxial growth (SEG) was used to obtain both high-speed and low-power performance for the SiGe HBTs. The process except the SEG is almost completely compatible with well-established Si bipolar-CMOS technology, and the SiGe HBT and BiCMOS were fabricated on a 200-mm wafer line. High-quality passive elements, i.e., high-precision poly-Si resistors, a high-Q varactor, an MIM capacitor, and high-Q spiral inductors have also been developed to meet the demand for integration of the sophisticated functions. A cutoff frequency of 130 GHz, a maximum oscillation frequency of 180 GHz, and an ECL gate-delay time of 5.3 ps have been demonstrated for the SiGe HBTs. An IC chipset for 40-Gb/s optical-fiber links, a single-chip 10-Gb/s transceiver large-scale IC (LSI), a 5.8-GHz electronic toll collection transceiver IC, and other practical circuits have been implemented by applying the SiGe HBT or BiCMOS technique.     

Si1—x—yGexCy材料的外延生长方法

本文分析了Si1 -x- yGexCy 半导体材料外延生长的困难所在 ,总结了用于生长Si1 -x- yGexCy材料的各种生长方法 ,并分析比较了各自的特点。     

La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs with high hole mobility and good device characteristics

We have studied high-k La/sub 2/O/sub 3/ p-MOSFETs on Si/sub 0.3/Ge/sub 0.7/ substrate. Nearly identical gate oxide current, capacitance density, and time-dependent dielectric breakdown (TDDB) are obtained for La/sub 2/O/sub 3//Si and La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ devices, indicating excellent Si/sub 0.3/Ge/sub 0.7/ quality without any side effects. The measured hole mobility in nitrided La/sub 2/O/sub 3//Si p-MOSFETs is 31 cm/sup 2//V-s and comparable with published data in nitrided HfO/sub 2//Si p-MOSFETs. In sharp contrast, a higher mobility of 55 cm/sup 2//V-s is measured in La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFET, an improvement by 1.8 times compared with La/sub 2/O/sub 3//Si control devices. The high mobility in Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs gives another step for integrating high-k gate dielectrics into the VLSI process.     

Gate-first Germanium nMOSFET with CVD HfO/sub 2/ gate dielectric and silicon surface passivation

A gate-first self-aligned Ge n-channel MOSFET (nMOSFET) with chemical vapor deposited (CVD) high-/spl kappa/ gate dielectric HfO/sub 2/ was demonstrated. By tuning the thickness of the ultrathin silicon-passivation layer on top of the germanium, it is found that increasing the silicon thickness helps to reduce the hysteresis, fixed charge in the gate dielectric, and interface trap density at the oxide/semiconductor interface. About 61% improvement in peak electron mobility of the Ge nMOSFET with a thick silicon-passivation layer over the CVD HfO/sub 2//Si system was achieved.