Design for Testability for Complete Test Coverage

Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achieve. This article presents DFT methods aimed at achieving total coverage. Two methods are compared: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation. The other method employs a test pattern generation algorithm (the FAN algorithm). Results show that 100 percent coverage within the allowed limits is difficult with the former approach. The latter, however, enables us to generate a test pattern for any detectable fault within the allowed time limits, and 100 percent test coverage is possible.     

一种低功耗系统芯片的可测试性设计方案

低功耗技术,如多电源多电压和电源关断等的应用,给现代超大规模系统芯片可测试性设计带来诸多问题。为此,采用工业界认可的电子设计自动化工具和常用的测试方法,构建实现可测试性设计的高效平台。基于该平台,提出一种包括扫描链设计、嵌入式存储器内建自测试和边界扫描设计的可测性设计实现方案。实验结果表明,该方案能高效、方便和准确地完成低功耗系统芯片的可测性设计,并成功地在自动测试仪上完成各种测试,组合逻辑和时序逻辑的扫描链测试覆盏率为98.2%。     

Macro Testing: Unifying IC And Board Test

Historically, IC testing and board testing have been considered two separate subjects. However, today's increasing complexity in both design and technology has given rise to a number of efforts to produce a consistent test strategy that smoothly couples both types of testing. This article describes one such effort by Philips, a design for testability methodology for semicustom VLSI circuits. The methodology is based on the partitioning of a design into testable macros, hence the term ?macro testing.? The challenges in this approach are the partitioning itself, the selection of a test technique suited to the separate macros and the chip's architecture, the execution of a macro test independent of its environment, and the assembly of macro tests into a chip test.     

基于边界扫描的电路板测试性优化设计

基于边界扫描的电路板测试性设计中，迫切需要解决“测试性改善程度一定时，如何权衡设计使得设计复杂性最小”的问题，本文首先深入分析了该问题，证明它是一个NP－ 完全问题，然后基于贪婪策略提出了求解问题的优化算法，仿真实验表明，该算法能够得较优化的电路板测试性设计方案。     

Synchronizing the IEEE 1149.1 test access port for chip leveltestability

IEEE STD 1149.9 is a widely accepted testability standard in the industry. Although its mandatory provisions focus narrowly on board level assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standard's TAP to be used at the system level for general system-level test and maintenance tasks and at the chip level for accessing chip-level testability features. Chip-level applications thus far have used the port for accessing the chip's scan design or for simple triggering of on-chip built-in self-test features via the RUNBIST instruction. Applications requiring general access to chipwide testability features that operate at the full chip-clock rate have been rare, primarily because of one of the standard's basic tenets-namely, its dedicated test clock. This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features     

Low Cost Scan Test by Test Correlation Utilization

Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suffer from prolonged test time and excessive test power due to numerous shift operations. The correlation among test data along with the high density of the unspecified bits in test data enables the utilization of the existing test data in the scan chain for the generation of the subsequent test stimulus, thus reducing both test time and test data volume. We propose a pair of scan approaches in this paper; in the first approach, a test stimulus partially consists of the preceding stimulus, while in the second approach, a test stimulus partially consists of the preceding test response bits. Both proposed scan-based test schemes access only a subset of scan cells for loading the subsequent test stimulus while freezing the remaining scan cells with the preceding test data, thus decreasing scan chain transitions during shift operations. The proposed scan architecture is coupled with test data manipulation techniques which include test stimuli ordering and partitioning algorithms, boosting test time reductions. The experimental results confirm that test time reductions exceeding 97%, and test power reductions exceeding 99% can be achieved by the proposed scan-based testing methodologies on larger ISCAS89 benchmark circuits.     

扫描设计中扫描链的优化

提出了扫描法可测性设计中扫描链的优化方法。采用交迭测试体制和区间法能快速求出最优解。对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。     

Testability transformation

A testability transformation is a source-to-source transformation that aims to improve the ability of a given test generation method to generate test data for the original program. We introduce testability transformation, demonstrating that it differs from traditional transformation, both theoretically and practically, while still allowing many traditional transformation rules to be applied. We illustrate the theory of testability transformation with an example application to evolutionary testing. An algorithm for flag removal is defined and results are presented from an empirical study which show how the algorithm improves both the performance of evolutionary test data generation and the adequacy level of the test data so-generated.     

基于雷达的测试性设计优化方法应用研究

基于雷达等电子产品测试性要求的不断提高,对产品进行测试性设计迭代并进行测试性验证,成为对电子产品的普遍要求。由于初始设计有缺陷、覆盖故障模式不全等引起测试性设计不能满足要求,开展闭环测试、脉冲检测、隔离策略优化等测试性改进,最终选择软、硬件改进相平衡的方案,通过回归试验,获得满足指标要求的检测率和隔离率结果,优化方法促进了产品的测试性设计改进和增长。     

数字集成电路的可测性设计及其应用

首先论述了可测性设计的概念，分析了时序电路测试生成面临的困境。然后介绍了可测性设计的专门方法，并举例说明了它在实际中的应用。     

单链扫描可测性设计中存储元件的排序

本文提出了扫描设计中存储元件在扫描链中的最优排序方法，采用交迭测试体制和区间法能快速求出最优解，对于确定的测试向量集，用该方法的构造的扫描链能使电路总的测试时间最少。     

可测试性设计技术在一款通用CPU芯片中的应用

可测试性设计(Design-For-Testability,简称DFT)是芯片设计的重要环节,它通过在芯片原始设计中插入各种用于提高芯片可测试性的硬件逻辑,从而使芯片变得容易测试,大幅度节省芯片测试的成本。文中介绍了在一款通用CPU芯片的设计过程中,为提高芯片的易测性而采取的各种可测试性设计技术,主要包括扫描设计(ScanDesign)、存储器内建自测试(Build-in-self-test,简称BIST)以及与IEEE1149.1标准兼容的边界扫描设计(BoundaryScanDesign,简称BSD)等技术。这些技术的使用为该芯片提供了方便可靠的测试方案。     

用于密码芯片的前馈异或安全扫描结构

扫描结构在给密码芯片增加可测性的同时也可能被不当使用为旁路攻击路径,使密码芯片的密钥信息泄露.为解决这个问题,提出一种前馈异或安全扫描结构.首先将异或安全扫描寄存器引入扫描结构中,该结构对测试图形进行输入?输出线性变换,实现对测试图形的硬件加密;然后分析了该结构的安全性并给出其测试图形生成算法.实验结果表明,文中提出的安全扫描结构能抗击基于扫描结构的旁路攻击和复位攻击,并保留了传统扫描结构的高测试覆盖率.     

IDDQ design and test advantages propel industry

The I_DDQ test method measures the quiescent power supply current of CMOS ICs for select test vectors, or logic states, and provides a clear indication of defects, failure mechanisms, and many types of design errors. Underlying this type of test are design principles that inherently provide high defect coverage, as well as diagnosis capability and physical localization. The ability of I_DDQ testing to rapidly gauge an IC's health is like a nurse taking a patient's temperature. This is an especially appropriate analogy because it underscores that I_DDQ testing is not a panacea. As with a patient, other "vital signs" are needed. The authors give a unique perspective into the design of a submicron-technology microprocessor (approximately 1 million transistor, 1OO MHz-plus design). Stringent testability and quality goals drove their selection of I_DDQ testing in addition to at-speed functional testing, boundary scan, internal scan, and built-in self-test. They demonstrate the many benefits of I_DDQ testing, including substantially reduced power consumption and the ability to merge readily with other testability and high-performance goals     

类蜂巢结构快速样机平台的可测试性设计

类蜂巢结构快速样机平台(HLRESP)是一个基于现场可编程门阵列(FPGA)的通用样机平台，采用类似蜂窝状的系统结构。根据该样机平台特点，采用边界扫描技术进行板级和系统级的可测试性设计，扫描链路可以灵活配置，不仅能实现边界扫描测试，还能实现对可编程器件的在线编程，方便了样机平台的测试和调试工作，缩短了系统开发周期。     

装备测试性设计辅助决策系统关键技术研究

针对测试性设计的辅助决策工具是装备测试性设计水平提高的关键技术。围绕测试性设计辅助决策系统实现,从装备测试性设计建模、装备测试性设计与分析优化算法、辅助决策系统实现等三个方面展开研究,在分析现有模型的基础上提出了用于测试性设计的信息模型建模思想,并对测试性设计过程中的诊断优化算法进行了研究,最后完成对测试性模型、诊断策略的集成,对系统平台实现的关键技术进行了研究。本研究是实现装备测试性设计辅助决策系统的关键。     

MCM 测试策略

首先分析了MCM的测试难度,针对“KGD”问题,阐述了电路在圆片级,小裸片级测试的构思和具体实施方法。讨论了基于边界扫描技术的测试方法,强调了可测试设计技术,从而提出了MCM的测试策略。     

边界扫描测试技术及其应用

边界扫描技术是一种完整的、标准化的可测性设计方法，它提供了对电路板上元件的功能、互连等进行测试的一种统一方案，极大地提高了系统测试的效率。本文详细介绍了边界扫描测试的原理、结构，讨论了边界扫描测试技术的应用。     

一个有效的不完全Scan结构MOS电路的测试生成算法

本文介绍一个不完全Scan结构MOS电路的测试生成算法DALG—EX18。该算法充分考虑不完全Scan结构的特点,同时也考虑MOS电路中由三态器件引出的一些特性,在传统5值D-算法基础上,引入18值及其计算规则,加入新的处理步骤,并辅以可观值/可控值引导D-驱赶和一致性操作,从而提高故障覆盖率,加快测试生成速度。DALG—EX18算法已用C语言在VAX 11/750机上实现,一些电路的实验结果表明,该算法是有效的。