Physical Understanding of Gate-Depletion Phenomena in Poly-Si/HfSiON Stacks Based on C–V Differentiation Analysis

We propose sub-1-A-resolution analysis of gate surface layer In scaled-T_inv (capacitance equivalent thickness at substrate inversion) gate stacks by differentiating their C-V curves. By introducing the universal derivative-of-capacitance curve, gate stacks with different equivalent oxide thickness of gate insulator and substrate-impurity concentration JVSub can be analyzed in one and the same plot. By applying this analysis technique to p+ poly-Si/HfSiON stack, it is found that gate depletion increases due to both lower poly impurity concentration N_poly and high pinning charge density N_ox inside the dielectric. Ultrathin SiN cap insertion onto HfSiON recovers the degradation in N_poly and N_ox leading to suppression of gate depletion and flatband voltage shift.     

Measurements and modeling of MOSFET I-V characteristics withpolysilicon depletion effect

The authors study the degradation of MOSFET current-voltage (V-I) characteristics as a function of polysilicon gate concentration (N_p ), oxide thickness (t_ox) and substrate impurity concentration (N_D) using measured and modeled results. Experimentally it is found that for MOSFETs with thin gate oxide (t_ox≈70 Å) and high substrate concentration (N_D ≈1.6×10¹⁷ cm^-3) the reduction in the drain current I_DS can be as large as 10% to 20% for devices with insufficiently doped polysilicon gate (5×10¹⁸ ⩽N_p⩽1.6×10¹⁹ cm^-3). Theoretically it is shown that the drain current degradation becomes more pronounced as N_p decreases, t_ox decreases, or N_D, increases. A modified Pao-Sah model that takes into account the polysilicon depletion effect and an accurate gate-field-dependent mobility model are used to compute I-V characteristics for various values of N_p, t_ox, and N_D. Good agreement between experimental and modeled results is observed over a wide range of devices     

A geometrical model of the threshold voltage of short and narrow channel MOSFETs

A simple geometrical model allows the calculation of the threshold voltage of short and narrow channel MOSFETs as a function of gate length, gate width, source and drain depth, substrate voltage and source drain voltage. Input parameters of the program are the customary values such as oxide thickness and, furthermore, an effective impurity concentration in the field region. The flat band voltage and the effective impurity concentration in the channel region can be calculated by a modified SUPREM program.     

Thickness dependence of boron penetration through O2 and N2O-grown gate oxides and its impact on threshold voltagevariation

We report on a quantitative study of boron penetration from p⁺ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O₂ or N₂O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model to predict the magnitude of boron penetration, N_B, for thicknesses other than those measured. We find that the minimum t_ox required to inhibit boron penetration is always 2-4 nm less when N₂O-grown gate oxides are used in place of O₂- grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in ULSI technologies. Because of the strong dependence of boron penetration on t_ox, incremental variations in oxide thickness result in a large variation in N_B , leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 10¹¹ cm^-2     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature     

A comparison of CVD stacked gate oxide and thermal gate oxide for0.5-μm transistors subjected to process-induced damage

Process-induced damage of gate oxide or of the Si-SiO₂ interface may result in device degradation problems such as threshold voltage scatter. The problem is especially pronounced for submicrometer technology. In addition to offering a low area defect density, a thermal/CVD stacked gate oxide decreases process-induced device degradation dramatically as compared with thermal gate oxide. Hot carrier injection stressing and Fowler-Nordheim stressing were performed to investigate the robustness of CVD stacked gate oxide. The effect of densification of the stacked gate oxide on electrical channel length was studied with supporting SEM analysis. An optimal value for the thickness ratio of CVD to thermal oxide for stacked gate dielectric was observed for minimum defect density of 150-Å gate dielectric     

Bias temperature instability in scaled p+ polysilicongate p-MOSFET's

The bias temperature instability in surface-channel p⁺ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (ΔV_th,BT) is induced by negative bias temperature (BT) stress in short-channel p⁺ polysilicon gate p-MOSFETs. This Vth shift, which depends on the gate length of p-MOSFETs, is a new degradation mode. In this degradation, the negative ΔV_th,BT increases significantly with a reduction in the gate length. It was shown that this is because of the local degradation of the gate oxide near the gate edge. This degradation is caused by the electrochemical reaction between holes and oxide defects and it is enhanced by boron penetration through the gate oxide from p⁺-gate. For the bias temperature instability in p⁺ -gate p-MOSFETs, sufficient care should be taken in scaled dual-gate CMOS devices     

Hydrogenated amorphous silicon thin-film transistor with a thingate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN_x and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm²/Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator     

Separation of hot-carrier-induced interface trap creation and oxidecharge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V_gs stress, HEIP is found to dominate the shift of threshold voltage V_t. When V_gs increases to a moderate value, the V_t shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V_gs is increased further to V_gs=V_ds. For the first time, the effects of interface trap creation and oxide charge trapping on the V_t shift are quantified by the proposed technique     

Influence of growth conditions of oxide on electrical properties of AlGaN/GaN metal–insulator–semiconductor transistors

AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors(MIS-HEMTs) on a silicon substrate were fabricated with silicon oxide as a gate dielectric by sputtering deposition and electron-beam(EB) evaporation. It was found that the oxide deposition method and conditions have great influences on the electrical properties of HEMTs. The low sputtering temperature or oxygen introduction at higher temperature results in a positive equivalent charge density at the oxide/AlGaN interface(Nequ), which induces a negative shift of threshold voltage and an increase in both sheet electron density(ns) and drain current density(ID). Contrarily, EB deposition makes a negative Nequ, resulting in reduced ns and ID. Besides, the maximum transconductance(gm-max) decreases and the off-state gate current density(I_G-off) increases for oxides at lower sputtering temperature compared with that at higher temperature, possibly due to a more serious sputter-induced damage and much larger Nequ at lower sputtering temperature. At high sputtering temperature, I_G-off decreases by two orders of magnitude compared to that without oxygen, which indicates that oxygen introduction and partial pressure depression of argon decreases the sputter-induced damage significantly. I_G-off for EB-evaporated samples is lower by orders of magnitude than that of sputtered ones, possibly attributed to the lower damage of EB evaporation to the barrier layer surface.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

Decrease of gate oxide dielectric constant in tungsten polycidegate processes

The gate oxide thickness for tungsten (W) polycide gate processes is studied, with tungsten silicide (WSi_x) deposited either by chemical vapor deposition (CVD) or sputtering. For WSi_x deposited by CVD, it is found that the effective thickness of gate oxide as determined by CV measurement increases in all cases if the annealing temperature is 900°C or higher. However, high-resolution transmission electron microscopy (TEM) measurement indicates that the physical thickness does not change after a 900°C anneal. In this case, the dielectric constant of the gate oxide decreases by 7%. As the annealing temperature increases to 1000°C, CV and TEM measurements give the same thickness and the decrease of the dielectric constant disappears. In contrast, for WSi_x film deposited by sputtering, annealing at 900°C has no effect on the gate oxide thickness as measured by CV and TEM     

Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

Effects of thermal processes after silicidation on the performanceof TiSi2/polysilicon gate device

The effects of thermal processes after silicidation on the gate depletion, threshold voltage (V_th) shift, drive current, and sheet resistance of TiSi₂/polysilicon (Ti-polycide) gate devices are evaluated. The dopant depletion of the polysilicon film, which is known to increase the V_th and to degrade the drive-current, increases with increasing temperature of the post-thermal process. However, the V_th roll-off characteristic in nMOSFETs is enhanced with increasing temperature. Furthermore, the drive-current is significantly degraded by the gate reoxidation process. The sheet resistance of the Ti-polycide gate increases with gate reoxidation as well as with increased post-thermal processes     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

A standby current limited performance figure of merit for deepsub-micron CMOS

The delay time of an inverter or NAND chain at a gate length yielding equal standby current and active current is used as the definition of a maximum Figure of Merit (FOM), FOM_max. The circuit power that occurs under this condition of equal standby and active currents is an equally important measure. This FOM_max technique is particularly useful in characterizing complementary metal-oxide-semiconductor (CMOS) technologies in the deep submicron regime. A knowledge of the exact value of gate length is not necessary to apply the FOM_max methodology. For a fixed supply voltage and gate oxide thickness, node capacitance and transistor drive, and off currents determine the value of FOM_max. The value of gate length at which FOM_max occurs decreases with decreasing supply voltage. FOM_max analysis is applied to the comparison of CMOS technologies using gate oxide thicknesses of 5.7 and 3.8 nm     

Suppression of the boron penetration induced Si/SiO2interface degradation by using a stacked-amorphous-silicon film as thegate structure for pMOSFET

The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO₂ interface. An atomically flat Si/SiO₂ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p⁺ poly-Si gate MOS devices even with the annealing temperature as high as 1000°C     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

pMOS dosimeter with two-layer gate oxide operated at zero andnegative bias

The linearity of threshold voltage shift, during irradiation of thick gate oxide pMOS transistors, operated at zero and negative bias, is investigated. It is found that the threshold voltage shift is not linear in the `zero bias regime'. The linearity increases with an increase in the absolute value of the negative gate voltage     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.