Low‐frequency noise analysis and minimization in Gilbert‐cell‐based mixers for direct‐conversion (zero‐IF) low‐power front‐ends

Low‐frequency (flicker) noise is one of the most important issues in the design of direct‐conversion zero‐IF front‐ends. Within the front‐end building blocks, the direct‐conversion mixer is critical in terms of flicker noise, since it performs the signal down‐conversion to baseband. This paper analyzes the main sources of low‐frequency noise in Gilbert‐cell‐based direct‐conversion mixers, and several issues for minimizing the flicker noise while keeping a good mixer performance in terms of gain, noise figure and power consumption are introduced in a quantitative manner. In order to verify these issues, a CMOS Gilbert‐cell‐based zero‐IF mixer has been fabricated and measured. A flicker noise as low as 10.4 dB is achieved (NF at 10 kHz) with a power consumption of only 2 mA from a 2.7 V power supply. More than 14.6 dB conversion gain and noise figure lower than 9 dB (DSB) are obtained from DC to 2.5 GHz with an LO power of ?10 dBm, which makes this mixer suitable for a multi‐standard low‐power zero‐IF front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐power design of CMOS baseband analog chain for direct conversion receiver

A low‐power CMOS receiver baseband analog (BBA) circuit based on alternating filter and gain stage is reported. For the given specifications of the BBA block, optimum allocation of the gain, input‐referred third‐order intercept point (IIP3), and noise figure (NF) of each block is performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in 0.18µm CMOS technology and IIP3 of 30 dBm with a maximum gain of 59 dB and NF of 31 dB are obtained at 3.6 mW power consumption. Copyright © 2008 John Wiley & Sons, Ltd.     

A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.     

A novel low‐power receiver topology for RF and microwave applications

A novel low‐power receiver topology for radio‐frequency and microwave applications is presented. The proposed solution exploits a simple connection between the low‐noise amplifier and the subsequent mixer, which is realized by means of a high‐value resistor and a current mirror, achieving low noise and high linearity performance with an extremely low power consumption. The criteria for its optimal design are derived in order to accomplish the main trade‐offs among noise figure (NF), linearity, and current consumption performance. As a case of study, the new topology has been designed in the case of I/Q direct conversion receiver for IEEE 802.15.4 standard (ZigBee) applications at 2.45 GHz. The receiver exhibits a NF of 8.7 dB, 50Ω input impedance, a voltage gain of 26 dB, an input‐referred third‐order intercept point of ?13 dBm, and a power consumption of 8.6 mW, which represent one of the best performance trade‐offs obtained in the literature. Copyright © 2008 John Wiley & Sons, Ltd.     

A linearized and low noise CMOS mixer with B‐type amplifier‐based sub‐harmonic balun

A low noise and high linearity down‐conversion CMOS mixer for 2.4‐GHz wireless receiver is presented in this paper. Using a sub‐harmonic balun with a simple but effective B‐type amplifier, the local oscillator frequency required for this mixer has been reduced by half, and the input local oscillator signal could be single‐ended rather than differential, which simultaneously simplifies the design of local oscillator. A distortion and noise cancelation transconductor in association with current bleeding technique is employed to improve the noise and linearity of the entire mixer under a reduced bias current without compromising the voltage gain. Fabricated in a 0.18‐µm RF CMOS technology of Global Foundries, the mixer demonstrates a voltage gain of 15.8 dB and input‐referred third‐order intercept point of 6.6 dBm with a noise figure of 2.6 dB. It consumes 7.65 mA from a 1.0‐V supply and occupies a compact area of 0.75 × 0.71 mm² including all test pads. Copyright © 2016 John Wiley & Sons, Ltd.     

Design and simulation of novel amplifier‐based mixer for ISM band wireless applications

This letter describes a low‐voltage low‐power (LV‐LP) 2.4‐GHz mixer for Industrial, Scientific and Medical (ISM) band wireless applications. The approach is based on a two‐stage amplifier, and the Gilbert switch stage is inserted between the two amplifier stages. The proposed amplifier‐based mixer delivers a remarkable conversion gain of 13 dB with a local oscillator (LO) power of 7 dBm, while consuming only 1.05‐mW DC power from a 0.8‐V supply voltage. The input‐referred third‐order intercept point (IIP3) of the mixer is 3.82 dBm, and the chip area is only 0.429 mm². The results indicate that this mixer is suitable for the low‐voltage low‐power applications. Copyright © 2014 John Wiley & Sons, Ltd.     

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

This paper presents an improved topology for ultra‐low‐power complementary metal oxide semiconductor (CMOS) distributed amplifier (DA) based on modified folded cascode gain cells. The proposed CMOS‐DA can be applicable in low‐supply‐voltage applications, because of the use of folded gain cell's structure. The proposed DA decreases power consumption by employing the forward body biasing network, while maintains high gain. By using a gain‐peaking inductor at the gate of the transistor, the proposed DA structure achieved to the gain flatness in high frequencies while the bandwidth is improved as well. In addition, employing RC network at the body terminal improves the noise performance of the proposed DA. The DA architecture consists of three amplification stages. Detailed analysis is provided for the proposed folded cascode DA. According to the post‐layout simulation results of the proposed amplifier using a 0.13‐µm CMOS process, DA achieves power gain of 17.3 ± 0.8 dB in bandwidth of 14.5 GHz, a good input third‐order intercept point (IIP3) of +5.5 dBm. The minimum noise figure is 1.8–5 dB, and input and output return losses are less than −11.5 dB and −10 dB, respectively, and the proposed structure consumes 12 mW from a 0.5 V voltage supply. Copyright © 2016 John Wiley & Sons, Ltd.     

DC–3 GHz low‐noise,flat‐gain‐response,and high‐linearity amplifier

This paper describes the design, fabrication, and testing of a DC–3 GHz ultra‐wideband low‐noise amplifier (LNA) using Avago ATF‐54143 enhanced‐mode pseudomorphic high‐electron mobility transistor. Negative feedback network is introduced to ensure unconditional stability of the LNA over the full waveband. Simulation results show that the LNA provides a gain varying between 14.872 and 14.052 dB, a noise figure (NF) of less than 2.2 dB, and voltage standing wave ratios (VSWRs) approaching 2. A high simulated output third‐order intercept point (OIP₃) of >30.2 dBm is achieved. In contrast, in 1‐dB bandwidth of DC–3 GHz, the measured gain is nominal at 13.10 dB. The obtained NF changes in a small range of 2–2.178 dB, and the measured VSWRs are no more than 1.64, which are better than obtained from simulation results. At the same time, OIP₃ at 1, 2, and 3 GHz is 30.3, 29.13, and 29.34 dBm, respectively, while the output at the 1‐dB compression point (P _1dB ) is 15.43, 14.83, and 14.33 dBm, respectively. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A duplex current‐reused CMOS LNA with complementary derivative superposition technique

A duplex current‐reused complementary metal–oxide–semiconductor low‐noise amplifier (LNA) is proposed for 2.5‐GHz application. The duplex current‐reused topology with equivalent three common‐source gain stages cascaded is utilized to fulfil the low‐power consumption and high gain simultaneously. The complementary derivative superposition linearization technique with bulk‐bias control is employed to improve the linearity performance with large‐signal swing and to extend the auxiliary transistors bias‐control range. The proposed LNA is fabricated in a 0.18‐um 1P5M complementary metal–oxide–semiconductor process and consumes a 3.13‐mA quiescent current from a 1.5 V voltage supply. The measurement results show that the proposed LNA achieves power gain of 28.1 dB, noise figure of 1.64 dB, input P1dB and IIP3 of −19.6 dBm and 3.2 dBm, respectively, while the input and output return loss is 19.2 dB and 18.4 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

Circuit and system design for an 860–960 MHz RFID reader front‐ends with Tx leakage suppression in 0.18 − µm CMOS technology

This paper presents an RF Front‐END for an 860–960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front‐end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front‐END contains a power amplifier (PA) in transmit chain and receive front‐end with low‐noise amplifier, up/down mixer, LP filter and variable‐gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18‐µm technology. The chip area is 2.65 mm × 1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power‐added efficiency of 24% with a power gain of 20 dB, including the losses of the bond‐wires. Copyright © 2011 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

Design of 3.1 to 10.6 GHz ultra‐wideband flat gain LNA

In this paper, a new ultra‐wideband low‐noise amplifier (LNA) is proposed. The proposed LNA has flat gain and low noise figure (NF) in the frequency range of 3.1 to 10.6 GHz. To obtain higher gain, cascode architecture is used. In this design, to have a lower NF, the noise cancellation technique applies to the cascode architecture. In addition, to have better matching at the input and output, active feedback and matching transistors are used, which also leads to better NF. To have flat gain, RLC load is used. In the proposed LNA, only one inductor is used, which leads to the smaller chip area. The proposed circuit is designed in 90 nm CMOS technology. The simulation shows NF of between 1.62 and 2.1 dB, flat gain between 11.9 and 12 dB and power consumption of 11.72 mW in the frequency range of 3.1 to 10.6 GHz. The simulation results support the theoretical predictions. Copyright © 2017 John Wiley & Sons, Ltd.     

Gain compression improvement on low‐power cascaded current reuse LNAs

Current reuse low‐noise‐amplifiers (CRLNAs) have been the norm to achieve high‐gain and low‐noise figure under low‐power budgets. However, conventional CRLNAs suffer from a severe lack of large‐signal linearity, especially in conventional cascaded CRLNAs. This main drawback is related with the typical biasing method imposed in the output stage. To prove our point, a large‐signal study is performed for a single stage common‐source in two distinct biasing situations: voltage biased and current biased. On the basis of the gathered results, a new CRLNA solution is proposed to relief the large‐signal bottleneck. The suggested design is analyzed in a 0.13 µm complementary metal–oxide–semiconductor (CMOS) standard process. Post‐layout simulations show 8 dB compression point improvement compared with the conventional CRLNA solution. The CRLNA draws a current of 650 μA from a 1.2 V supply. At 2.45 GHz, a power gain of 25.3 dB and a NF of 2.3 dB are achieved, while the IIP3 is ?9 dBm. Copyright © 2016 John Wiley & Sons, Ltd.     

Design and analysis of a millimeter‐wave injection locked frequency divider with transconductance boosting technique

This paper presents a degenerated injector (mixer) with transconductance boosted by biasing the mixer transistor in the knee region of its I‐V curve, without increasing the transistor size and its parasitics. This mixer can enhance the locking range of millimeter‐wave injection‐locked frequency dividers. To compensate the degradation of mixer transconductance (conversion‐gain) due to the degeneration effect, a neutralization technique is employed. Analyses are given for locking‐range and induced phase‐noise of the proposed divider for arbitrary injection strength. It is shown that the locking‐range, as a function of injection strength, is improved by increasing the fundamental component of transconductance. Using 180‐nm CMOS technology, a 1.78‐mW divider‐by‐two is designed with free‐running frequency of 27.92 GHz, locking‐range of 51 to 59.6 GHz, and figure‐of‐merit of 4.83 (GHz/mW). EM simulation results of the proposed and conventional structure are compared, which illustrates 56% improvement in locking‐range.     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.     

A UWB receiver with modified CS-CG LNTA: Noise and nonlinearity analysis

A modified common source-common gate (CS-CG) low-noise transconductance amplifier (LNTA) with an improved noise figure (NF), operational bandwidth, and power consumption are analyzed in this paper. The common source (CS) stage of the modified LNTA is utilized for noise cancellation and transconductance enhancement of the common gate (CG) transistor. Using these, NF, bandwidth, and power consumption are improved without using extra active elements. Noise analyses show the modified CS-CG LNTA has lower NF than conventional CS-CG LNTA. The linearity of the modified CS-CG LNTA is calculated by Taylor series expression. Besides, a design procedure is proposed based on the obtained equations for linearity and NF. Finally, an ultra-wideband (UWB) surface acoustic wave (SAW-less) direct-conversion receiver is designed in 65 nm complementary metal-oxide-semiconductor (CMOS) technology. NF and third-order intercept point (IIP3) of the designed receiver are simulated as 5 dB and −2 dBm, respectively. The receiver consumes 18.4 mA from a 1.8 V supply voltage.     

Base coupled differential amplifier: a new topology for RF integrated LNA

A new topology of bipolar low noise amplifier (LNA) for RF applications, named base coupled differential (BCD), is presented. The proposed approach is compared by simulation against most classical topologies. The BCD configuration has the key advantage to join an integrated matching on a single‐ended input with a differential output. This is done by using down‐bond wiring, so that no integrated inductors are needed. The main advantages of this new topology are a drastic area reduction and an increased linearity range (or a reduced biasing current with the same linearity) together with a noise figure (NF) and voltage supply reduction. Particularly, the BCD LNA presented in this paper has been designed for 2.44GHz frequency operation. It is characterized by a NF of 1.93dB, a voltage gain (Av) of 19.5dB, an input impedance of 50Ωa third Input‐referred Intercept Point (IIP3) of ‐7.25dBm and a dissipated power (PD) equal to 19mW. Copyright © 2003 John Wiley & Sons, Ltd.     

360-μW 4.1-dB NF CMOS MedRadio receiver RF front-end with current-reuse Q-boosted resistive feedback LNA for biomedical IoT applications

In this paper, a low-power low-noise complementary metal-oxide semiconductor (CMOS) receiver RF front-end (RFFE) that employs a current-reuse Q-boosted resistive feedback low-noise amplifier (RFLNA) is proposed for 401 to 406 MHz medical device radio-communication service band IoT applications. By employing a series RLC input matching network, the proposed RFLNA has the advantages of both the conventional RFLNA and the inductively degenerated common-source LNA without using large on-chip spiral inductors at the sources of the main transistors. The proposed active mixer utilizes a current-reuse transconductor, in which a p-channel metal-oxide semiconductor (PMOS) transistor performs a current-bleeding function to reduce direct current (DC) and flicker noise in the switching stage of the active mixer. The proposed receiver RFFE is implemented in a 65-nm CMOS process and achieves a voltage gain of 30.9 dB, noise figure of 4.1 dB, S11 of less than −10 dB, and IIP3 of −22.9 dBm. It operates at a supply voltage of 1 V with bias currents of 360 μA. The active die area is 0.4 mm × 0.35 mm.     

A 40 M–1000 MHz 77.2‐dB spurious free dynamic range CMOS RF variable gain amplifier for digital TV tuner ICs

In this paper, a 40 M–1000 MHz 77.2‐dB spurious free dynamic range (SFDR) CMOS RF variable gain amplifier (VGA) has been presented for digital TV tuner applications. The proposed RFVGA adopts a wideband operational‐amplifier‐based VGA and a wideband buffer with differential multiple gated transistor linearization method for wideband operation and high linearity. The SFDR of the proposed RFVGA is also analyzed in detail. Fabricated in a 0.13‐µm CMOS process, the RFVGA provides 31‐dB gain range with 1‐dB gain step, a minimum noise figure of 7.5 dB at a maximum gain of 27 dB, and maximum in‐band output‐referred third‐order intercept point of 27.7 dBm, while drawing an average current of 27.8 mA with a supply voltage of 3.3 V. The chip core area is 0.54 mm × 0.4 mm. Copyright © 2014 John Wiley & Sons, Ltd.