A 16-Mb Toggle MRAM With Burst Modes

This paper describes a recently developed 16-Mb toggle magnetic random access memory (MRAM). It has 100-MHz burst modes that are compatible with a pseudo-SRAM even though the toggle cell requires reading and comparing sequences in write modes. To accelerate operating clock frequency, we propose a distributed-driver wide-swing current-mirror scheme, an interleaved and pipelined memory-array group activation scheme, and a noise-insulation switch scheme. These circuit schemes compensate the toggle cell timing overhead in write modes and maintain write-current precision that is essential for the wide operational margin of MRAMs. Because toggle cells are very resistant to write disturbance errors, we designed the 16-Mb MRAM to include a toggle MRAM cell. The MRAM was fabricated with 0.13-mum CMOS and 0.24-mum MRAM processes with five metal layers.     

A 16-ns 1-Mb CMOS EPROM

A 16-ns 1-Mb CMOS EPROM has been developed utilizing high-speed circuit technology and a double-metal process. In order to achieve the fast access time, a differential sensing scheme with address transition detection (ATD) is used. A double-word-line structure is used to reduce word-line delay. High noise immunity is obtained by a bit-line bias circuit and data-latch circuit. Sufficient threshold voltage shift (indispensable for fast access time) is guaranteed by a threshold monitoring program (TMP) scheme. The array is organized as 64 K×16 b, which is suitable for 32-b high-performance microprocessors. The active power is 425 mW, the programming time is 100 μs, and the chip size is 4.94×15.64 mm²     

A 3.3-V 12-ns 16-Mb CMOS SRAM

A 16-Mb CMOS SRAM having an access time of 12 ns under a 3.3-V supply has been developed with a 0.4-μm process technology. An address access time of 12 ns has been achieved by an optimized architecture, the use of an automated transistor size optimizer, and a read-bus midlevel preset scheme (RBMIPS). For better yield and efficient testing, an on-chip test circuit with three test modes has been implemented     

A circuit technology for high-speed battery-operated 16-Mb CMOSDRAM's

A battery-operated 16-Mb CMOS DRAM with address multiplexing has been developed by using an existing 0.5-μm CMOS technology. It can access data in 36 ns when powered from a 1.8-V battery-source, and 20 ns at 3.3 V. However, this device requires a mere 57 mA of operating current for an 80-ns cycle time and only 5 μA of standby current at 3.3 V. To achieve both high-speed and low-power operation, the following four circuit techniques have been developed: 1) a parallel column access redundancy (PCAR) scheme coupled with a current sensing address comparator (CSAC), 2) an N&PMOS cross-coupled read-bus-amplifier (NPCA), 3) a gate isolated sense amplifier (GISA) with low V_T, and 4) a layout that minimizes the length of the signal path by employing the lead on chip (LOC) assembly technique     

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layoutsense amplifiers

A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm² is fabricated and an address access time of 12.5 ns has been achieved     

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro

We have used a 5-metal 0.18-μm CMOS logic process to develop a 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. The macro contains: (1) end-point dual-pulse drivers for accurate timing control; (2) a wordline-voltage-level compensation circuit for stable data retention; and (3) an all-adjoining twisted bitline scheme for reduced bitline coupling capacitance. The macro is capable of 400-MHz high-speed access at 1.8-V supply voltage and is 66% the size of a conventional six-transistor SRAM macro. We have also developed a higher-performance 500-MHz loadless four-transistor SRAM macro in a CMOS process using 0.13-μm gate length     

A 34-ns 16-Mb DRAM with controllable voltage down-converter

A high-speed 16-Mb DRAM with high reliability is reported. A multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme were used to meet the requirements for high speed. A low-power hybrid internal power supply voltage converter with an accelerated life-test function is also proposed and was demonstrated. A novel substrate engineering technology, a retrograded well structure formed by a megaelectronvolt ion-implantation process, provides a simple process sequence and high reliability in terms of soft error and latch-up immunity.<>     

A 1.8-V 128-Mb 125-MHz multilevel cell flash memory with flexible read while write

Application of multilevel cell (MLC) technology to a flexible read-while-write flash memory has been achieved through the use of a highly optimized sensing architecture. The goal of this implementation is to provide performance on par with single-bit-per-cell implementations while significantly reducing the overall die size. In order to achieve the required high-speed operation using MLC structures, all offsets to the sense amplifier were minimized and the column load and local sense amplifier were optimized to provide ample differential gain. Through the use of these optimization techniques, a 1.8-V MLC-based flexible read-while-write memory with 125-MHz continuous burst and 40-ns random read access time has been manufactured. Using a 0.13-/spl mu/m technology, this new device provides a die size that is 25% of the size of the equivalent single-bit-per-cell device manufactured on a 0.18-/spl mu/m technology.     

A new erasing and row decoding scheme for low supply voltageoperation 16-Mb/64-Mb flash memories

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories     

A 9-ns 16-Mb CMOS SRAM with offset-compensated current senseamplifier

A 9-ns 16-Mb CMOS SRAM has been developed using a 0.35-μm CMOS process, The current-mode fully nonequalized data path has been realized in a CMOS SRAM for the first time by using a stabilized feedback current-sense amplifier (SFCA) that provides a small input resistance and an offset compensation effect. To reduce the test time, a bit-line wired-OR parallel test circuit has been implemented     

A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture

Circuit techniques for a reduced-voltage-amplitude data bus, fast access 16-Mb CMOS SRAM are described. An interdigitated bit-line architecture reduces data bus line length, thus minimizing bus capacitance. A hierarchical sense amplifier consists of 32 local sense amplifiers and a current sense amplifier. The current sense amplifier is used to reduce the data bus voltage amplitude and the sensing of the 16-b data bus signals in parallel. Access time of 15 ns and an active power of 165 mW were achieved in a 16-Mb CMOS SRAM. A split-word-line layout memory cell with double-gate pMOS thin-film transistors (TFTs) keeps the transistor width stable while providing high-stability memory cell characteristics. The double-gate pMOS TFT also increases cell-storage node capacitance and soft-error immunity     

A 5-V-only 16-Mb flash memory with sector erase mode

A 5-V-only 16-Mb CMOS flash memory with sector erase mode is described. An optimized memory cell with diffusion self-aligned drain structure and channel erase are keys to achieving 5-V-only operation. By adopting this erase method and row decoders to apply negative bias, 512-word sector erase can be realized. The auto chip erase time of 4 s has been achieved by adopting 64-b simultaneous operation and improved erase sequence. The cell size is 1.7 μm×2.0 μm and the chip size is 6.3 mm×18.5 mm using 0.6-μm double-layer metal triple-well CMOS technology     

A 60-ns 16-Mb flash EEPROM with program and erase sequencecontroller

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm×2.0 μm and a chip size of 6.5 mm×18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process     

A 55-ns 16-Mb DRAM with built-in self-test function usingmicroprogram ROM

A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55-μm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm² chip area was attained by implementing 4.05-μm² storage cells. The installed ROM was composed of 18 words×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm² and the area overhead is about 1%, it proves to be promising for large-scale DRAMs     

A 90-MHz 16-Mb system integrated memory with direct interface toCPU

This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. Also fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-μm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3 mm² is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-bit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants (PDA's), personal computer systems, and embedded controller applications     

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

A low-voltage high-speed 16-Mb SOI-DRAM has been developed using a 0.5-μm CMOS/SIMOX technology. A newly introduced “FD-PD mode switching” transistor dynamically switches its operation mode between fully depleted (FD) and partially depleted (PD) according to the body bias voltage, thus it has both PD-mode large current drivability and FD-mode small leakage current. By the body bias control, the transistor operates as if it has an S-factor of 30 mV/decade. Enabling both high speed and low power at a low voltage, 30 mV is only one-half the theoretical value. By utilizing the transistor, we have developed body pulsed sense amplifier (BPS), body driven equalizer (BDEQ), body current clamper (BCC), and body pulsed transistor logic (BPTL) to achieve 46 ns access time at 1 V power supply with suppressed standby current     

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportionalself-timing generator

This 512 Kw×8 b×3 way synchronous BiCMOS SRAM uses a 2-stage wave-pipeline scheme, a PLL self-timing generator and a 0.4-μm BiCMOS process to achieve 220 MHz fully-random read/write operations with a GTL I/O interface. Newly developed circuit technologies include: 1) a zig-zag double word-line scheme, 2) a centered bit-line load layout scheme, and 3) a phase-locked-loop (PLL) with a multistage-tapped ring oscillator which generates a clock cycle proportional pulse (CCPP) and a clock edge lookahead pulse (CELP)     

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique

To meet the increasing demand for higher-density and faster EPROMs, a 16-Mb CMOS EPROM has been developed based on 0.6-μm N-well CMOS technology. In scaled EPROMs, it is important to guarantee device reliability under high-voltage operation during programming. By employing internal programming-voltage reduction and new stress relaxation circuits, it is possible to keep an external programming voltage V_pp of 12.5 V. The device achieves a 62-ns access time with a 12-mA operating current. A sense-line equalization and data-out latching scheme, made possible by address transition detection (ATD), and a bit-line bias circuit with two types of depletion load led to the fast access time with high noise immunity. This 16-Mb EPROM has pin compatibility with a standard 16-Mb mask-programmable ROM (MROM) and is operative in either word-wide or byte-wide READ mode. Cell size and chip size are 2.2 μm×1.75 μm and 7.18 mm×17.39 mm, respectively     

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-μm CMOS triple-well quad-metal technology. The videophone LSI is applied to the 3GPP 3G-324M video-telephony standard for IMT-2000, and implements the MPEG-4 video SPL1 codec, the AMR speech codec, and the ITU-T H.223 Annex B multiplexing/demultiplexing at the same time. Three 16-bit multimedia-extended RISC processors, dedicated hardware accelerators, and a 16-Mb embedded DRAM are integrated on a 10.84 mm×10.84 mm die. It also integrates camera, display, audio, and network interfaces required for a mobile video-phone terminal. In addition to conventional low-power techniques, such as clock gating and parallel operation, some new low-power techniques are also employed. These include an embedded DRAM with optimized configuration, a low-power motion estimator, and the adoption of the variable-threshold voltage CMOS (VT-CMOS). The MPEG-4 videophone LSI consumes 240 mW at 60 MHz, which is only 22% of that for a conventional multichip design. Variable threshold voltage CMOS reduces standby leakage current to 26 μA, which is only 17% of that for the conventional CMOS design     

A 16-Mb flash EEPROM with a new self-data-refresh scheme for asector erase operation

A 16-Mb flash EEPROM has been developed based on the 0.6-μm triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 μm×1.7 μm, resulting in a die size of 7.7 mm×17.32 mm