Planar Thermoelectric Microgenerators Based on Silicon Nanowires

Silicon nanowires have been implemented in microfabricated structures to develop planar thermoelectric microgenerators (??TEGs) monolithically integrated in silicon to convert heat flow from thermal gradients naturally present in the environment into electrical energy. The compatibility of typical microfabrication technologies and the vapor?Cliquid?Csolid (VLS) mechanism employed for silicon nanowire growth has been evaluated. Low-thermal-mass suspended structures have been designed, simulated, and microfabricated on silicon-on-insulator substrates to passively generate thermal gradients and operate as microgenerators using silicon nanowires as thermoelectric material. Both electrical measurements to evaluate the connectivity of the nanowires and thermoreflectance imaging to determine the heat transfer along the device have been employed.     

High-Temperature Performance of Stacked Silicon Nanowires for Thermoelectric Power Generation

Deep reactive-ion etching at cryogenic temperatures (cryo-DRIE) has been used to produce arrays of silicon nanowires (NWs) for thermoelectric (TE) power generation devices. Using cryo-DRIE, we were able to fabricate NWs of large aspect ratios (up to 32) using a photoresist mask. Roughening of the NW sidewalls occurred, which has been recognized as beneficial for low thermal conductivity. Generated NWs, which were 7 μm in length and 220 nm to 270 nm in diameter, were robust enough to be stacked with a bulk silicon chip as a common top contact to the NWs. Mechanical support of the NW array, which can be created by filling the free space between the NWs using silicon oxide or polyimide, was not required. The Seebeck voltage, measured across multiple stacks of up to 16 bulk silicon dies, revealed negligible thermal interface resistance. With stacked silicon NWs, we observed Seebeck voltages that were an order of magnitude higher than those observed for bulk silicon. Degradation of the TE performance of silicon NWs was not observed for temperatures up to 470°C and temperature gradients up to 170 K.     

Improvement of interface quality by post-annealing on silicon nanowire MOSFET devices with multi-wire channels

We have investigated the passivation effects of high-pressure hydrogen annealing (HPHA) on silicon nanowire (Si NW) metal oxide semiconductor field effect transistors (MOSFETs) with multi-wire channels. Compared to the conventional forming gas annealing (FGA) process, the results show that HPHA can significantly improve device performance parameters such as threshold voltage, subthreshold slope, mobility, and I_ON/I_OFF ratio. This enhancement is attributed to the effective passivation of the interface traps between the SiO₂ and the Si NW channel. Therefore, HPHA can be a promising process for the implementation of the Si NW MOSFET.     

Selective vapor-liquid-solid epitaxial growth of micro-Si probe electrode arrays with on-chip MOSFETs on Si (111) substrates

This paper reports on a fabrication technique for realizing micro-Si probe arrays with MOSFETs on the same Si substrate. Micro-Si probe arrays have been successfully fabricated on Si (111) substrates by selective vapor-liquid-solid (VLS) growth using catalytic Au dot arrays and Si/sub 2/H/sub 6/ used as the gas source for a molecular-beam-epitaxy. The Si probes can be grown at temperatures ranging from 500/spl deg/C to 700/spl deg/C. In this paper, MOSFETs were fabricated on Si (111) substrates and Au dots were placed at the drain regions of the MOSFETs in order to grow the Si probes. VLS growth at 700/spl deg/C for 2 h was carried out on these substrates. Consequently, the MOSFETs can be used in on-chip circuits for the VLS-Si probe array. The electrical characteristics of the MOSFETs were measured before and after the VLS process. After the VLS process, no changes in the MOSFET characteristics were observed due to the effects of Au-diffusion, and the results confirmed that VLS growth at a temperature of 700/spl deg/C allows fabrication of micro-Si probes without deterioration of the MOSFETs. VLS-Si probes with controlled conductance were realized. The as-grown Si probes were of high resistance, but could be changed to various conductivities by impurity diffusion.     

Highly Ordered Vertical Silicon Nanowire Array Composite Thin Films for Thermoelectric Devices

The fabrication and characterization of silicon nanowire (NW) array/spin-on glass (SOG) composite films for thermoelectric devices are presented. Interference lithography was used to pattern square lattice photoresist templates over entire 2 cm × 2 cm n-type Si substrates. The photoresist pattern was transferred to a SiO₂ hard mask for a single-step deep reactive ion Si etch. The resulting Si NW arrays were 1 μm tall with 15% packing density, and the individual NWs had diameters of 80 nm to 90 nm with vertical sidewalls. The Si NW arrays were embedded in SOG to form a dense and robust composite material for device fabrication and thin-film characterization. The thermal conductivity of the Si NW/SOG composite film was measured to be a constant 1.45 ± 0.2 W/m-K from 300 K to 450 K. An effective medium model was then used to extract a thermal conductivity of 7.5 ± 1.7 W/m-K for the Si nanowires from the measured Si NW/SOG values. The cross-plane Seebeck coefficient of the Si NWs was measured to be −284 ± 26 μV/K, which is comparable to −310 μV/K for bulk Si. Power generation from the combined Si NW/SOG and substrate devices is also presented, and the maximum generated power was found to be 29.3 μW with ΔT of 56 K for a 50 μm × 50 μm device.     

Self-Assembled Germanium Quantum-Dot Supercrystals in Silicon with Extremely Low Thermal Conductivities for Thermoelectrics

Superlattices with one-dimensional (1D) phonon confinement were studied to obtain a low thermal conductivity for thermoelectrics. Since they are composed of materials with a lattice mismatch, they often show dislocations. Like 1D nanowires, they also decrease heat transport in only one main propagation direction. It is therefore challenging to design superlattices with a thermoelectric figure of merit ZT higher than unity. Epitaxial self-assembly is a major technology to fabricate three-dimensional (3D) Ge quantum-dot (QD) arrays in Si. They have been used for quantum and solar-energy devices. Using the atomic-scale phononic crystal model, 3D Ge QD supercrystals in Si also present an extreme reduction of the thermal conductivity to a value that can be under 0.04 W/m/K. Owing to incoherent phonon scattering, the same conclusion holds for 3D supercrystals with moderate QD disordering. As a result, they might be considered for the design of highly efficient complementary metal–oxide–semiconductor (CMOS)-compatible thermoelectric devices with ZT possibly much higher than unity. Such a small thermal conductivity was only obtained for two-dimensional layered WSe₂ crystals in an experimental study. However, electronic conduction in the Si/Ge compounds is significantly enhanced. The 0.04 W/m/K value can be computed for different Ge QD filling ratios of the Si/Ge supercrystal with size parameters in the range of current fabrication technologies.     

Hierarchical Shelled ZnO Structures Made of Bunched Nanowire Arrays

The size‐ and morphology‐controlled growth of ZnO nanowire (NW) arrays is potentially of interest for the design of advanced catalysts and nanodevices. By adjusting the reaction temperature, shelled structures of ZnO made of bunched ZnO NW arrays are prepared, grown out of metallic Zn microspheres through a wet‐chemical route in a closed Teflon reactor. In this process, ZnO NWs are nucleated and subsequently grown into NWs on the surfaces of the microspheres as well as in strong alkali solution under the condition of the pre‐existence of zincate (ZnO₂^2–) ions. At a higher temperature (200 °C), three different types of bunched ZnO NW or sub‐micrometer rodlike (SMR) aggregates are observed. At room temperature, however, the bunched ZnO NW arrays are found only to occur on the Zn microsphere surface, while double‐pyramid‐shaped or rhombus‐shaped ZnO particles are formed in solution. The ZnO NWs exhibit an ultrathin structure with a length of ca. 500 nm and a diameter of ca. 10 nm. The phenomenon may be well understood by the temperature‐dependent growth process involved in different nucleation sources. A growth mechanism has been proposed in which the degree of ZnO₂^2–saturation in the reaction solution plays a key role in controlling the nucleation and growth of the ZnO NWs or SMRs as well as in oxidizing the metallic Zn microspheres. Based on this consideration, ultrathin ZnO NW cluster arrays on the Zn microspheres are successfully obtained. Raman spectroscopy and photoluminescence measurements of the ultrathin ZnO NW cluster arrays have also been performed.     

热氧化方法制备直径可控的有序硅纳米线阵列

采用金属辅助化学刻蚀方法结合纳米球模板技术制备出了有序硅纳米线阵列.硅纳米线阵列经过高温热氧化形成一定厚度的氧化层,再使用稀释的HF溶液去除表面氧化层得到可控直径/周期比、低孔隙密度的有序纳米线阵列.主要研究了氧化温度、氧化时间对硅纳米线形貌的影响,并根据扩展的Deal-Grove模型计算了硅纳米线氧化层厚度与氧化时间的关系,讨论了氧化过程中应力分布的影响,理论计算结果与实验结果一致.最后,采用两步氧化的方法制备出了低直径/周期比(约0.1)、低孔隙密度的有序硅纳米线阵列.     

Thermoelectric Power of Different Phases and States of Silicon at High Pressure

The thermoelectric properties of silicon in its high-pressure and metastable (upon decompression) phases in the pressure range up to ～25 GPa were investigated. Experimental data were obtained using designed high-pressure cells with sintered diamond anvils. Band-structure calculations based on density functional theory were performed to explain the thermoelectric properties. In particular, it has been established that the nonnegligible positive values of the thermoelectric power S found for the high-pressure “metal” phases of silicon may be well explained by s–d electron scattering. Qualitative agreement between the experimental data and the results of the calculations has been achieved for the known silicon polymorphs named Si-III, Si-V, and Si-XI.     

Silicon in functional epitaxial oxides: A new group of nanostructures

The ability to integrate low-dimensional crystalline silicon into crystalline insulators with high dielectric constant (high-k) can open the way for a variety of novel applications ranging from high-k replacement in future nonvolatile memory devices to insulator/Si/insulator structures for nanoelectronic applications. We will present an approach for nanostructure fabrication by incorporation of crystalline silicon into epitaxial oxide that is based on a solid-phase epitaxy of Si. In dependence on the preparation conditions we obtained nanostructures containing an either ultra-thin single-crystalline Si quantum-well buried in single-crystalline oxide matrix with sharp interfaces or Si-nanocrystals (ncs) embedded into single-crystalline oxide layer. As an example, we demonstrate the growth of Si buried in Gd₂O₃ and the incorporation of epitaxial Si clusters into single-crystalline Gd₂O₃ on silicon as well as silicon carbide substrates using molecular beam epitaxy. The leakage current of the obtained nanostructures exhibited negative differential resistance at lower temperatures. For structures containing Si-ncs a large hysteresis in capacitance–voltage measurements due to charging and discharging of the Si-ncs was obtained.     

Nanograin Effects on the Thermoelectric Properties of Poly-Si Nanowires

In this work we perform a theoretical analysis of the thermoelectric performance of polycrystalline Si nanowires (NWs) by considering both electron and phonon transport. The simulations are calibrated with experimental data from monocrystalline and polycrystalline structures. We show that heavily doped polycrystalline NW structures with grain size below 100 nm might offer an alternative approach to achieve simultaneous thermal conductivity reduction and power factor improvements through improvements in the Seebeck coefficient. We find that deviations from the homogeneity of the channel and/or reduction in the diameter may provide strong reduction in the thermal conductivity. Interestingly, our calculations show that the Seebeck coefficient and consequently the power factor can be improved significantly once the polycrystalline geometry is properly optimized, while avoiding strong reduction in the electrical conductivity. In such a way, ZT values even higher than the ones reported for monocrystalline Si NWs can be achieved.     

The Nanometer-Sized Eutectic Structure of Si/CrSi<Subscript>2</Subscript> Thermoelectric Materials Fabricated by Rapid Solidification

Nanostructuring is known to be an effective method to improve thermoelectric performance but, generally, it requires complex procedures and much labor. In the present study, self-assembled nanometer-sized composite structures of silicon (Si) and chromium disilicide (CrSi₂) were easily fabricated by the rapid solidification of a melt with a eutectic composition. Ribbon-like samples were obtained with a dominant nanostructure of fine aligned lamellae with a spacing range of 20–35 nm. The thermoelectric power factor of the ribbon was observed to be 1.2 mW/mK² at room temperature and reached 3.0 mW/mK² at 773 K. The thermal conductivity was 65% lower than that of a bulk eutectic sample. The results suggest that this method is promising for fabricating an effective nanostructure for thermoelectric performance.     

High efficiency n-ZnO/p-Si core–shell nanowire photodiode based on well-ordered Si nanowire array with smooth surface

A highly efficient n-ZnO/p-Si core–shell nanowire (NW) photodiode was fabricated using ZnO grown by atomic layer deposition (ALD) on a well-ordered Si NW array. Si NW arrays were prepared by metal-assisted chemical etching, for which a metal mesh with a well-organized nanohole array was made using anodic aluminum oxide. This resulted in a good arrangement, smooth surface, and small diameter distribution of the Si NW array. Consequently, ZnO layers with various thicknesses from 15 to 30 nm were deposited by the ALD method. Because of the smooth surface of the well-ordered Si NWs yielding low surface roughness scattering, the resulting photodiode showed significantly improved device characteristics.     

Thermoelectric effects in nanoscale layers of manganese silicide

The values of the thermoelectric power, layer resistivity and thermal conductivity of a Mn _x Si_1–x nanoscale layer and Mn _x Si_1–x/Si superlattice on silicon depending on the growth temperature in the range T = 300–600 K are found experimentally. The contribution of the nanoscale film and substrate to the thermoelectric effect is discussed. The thermoelectric figure of merit of a single manganese-ssilicide layer, superlattice, and layer/substrate system is estimated. The largest figure of merit ZT = 0.59 ± 0.06 is found for Mn_0.2Si_0.8 at T = 600 K.     

Dependence of the efficiency of Raman scattering in silicon nanowire arrays on the excitation wavelength

The features of Raman scattering in layers of silicon nanowires from 50 to 350 nm in diameter, obtained by the chemical etching of crystalline silicon (c-Si) wafers with preliminarily deposited silver nanoparticles in fluoric acid solutions are studied. c-Si wafers with various crystallographic orientations and doping levels are used, which is conditioned by the different sizes and degrees of ordering of the formed nanostructures. It is found that the radiation of the Raman scattering of samples is depolarized, and its efficiency depends strongly on the excitation wavelength. Upon excitation by light with a wavelength of 1064 nm, the ratio of Raman-scattering intensities of silicon nanowire samples and c-Si is 2 to 5; as the wavelength decreases, this ratio increases for structures with larger silicon-nanowire diameters and higher degrees of ordering and decreases for less ordered structures. The results obtained are explained by the effect of partial light localization in silicon nanowire arrays.     

Nanoporous black multi-crystalline silicon solar cells: realization of low reflectance and explanation of high recombination loss

Nanoporous black silicon (nb–Si) structures with/without saw damage removal (SDR) on solar-grade multi-crystalline silicon substrates have been formed by simple Ag-induced chemical etching. The  nb–Si shows a unique morphology of nano-scale holes on micron-scale patterns with low reflectance (<5%). The photovoltaic properties of nb–Si solar cells show that SDR process prior to Ag-induced chemical etching is an effective way to lower recombination and ohmic losses, resulting in significant efficiency enhancement of 26.0%. To further reduce the recombination loss for the nb–Si solar cells with ～10% efficiency, a two-layer emitter model has been introduced to explain the reduced emitter diffusion length that significantly lower spectral response. This suggests that removing residual Ag nanoparticles completely might be the key approach to enhance the spectral response of nb–Si solar cells with very low surface reflectance, thus increasing the final conversion efficiency.     

The High-Temperature Thermoelectric Properties of Polycrystalline Ba8Ga x Al y Si46−x−y Type-I Clathrates

Thermoelectric materials suitable for practical thermoelectric power generators should, ideally, be based on light elements, for example Si and Al, which are abundantly available. For this reason, silicon clathrate compounds in which both Ga and Al were substituted for Si were synthesized and their thermoelectric properties were investigated. The temperature-dependent electrical resistivity of the samples indicated their metallic nature, and their negative Seebeck coefficient suggested that charge transport in the samples was mainly through electron transport. The maximum absolute value of the Seebeck coefficient achieved was ?180 μV/K at 1040 K for Ba_7.90Ga_13.8Al_2.29Si_30.0. Thus, these materials have potential for use in practical thermoelectric power generators.     

Effects of surface passivation in porous silicon as H2 gas sensor

This paper investigates the effects of surface passivation in porous silicon (PS) as a hydrogen gas sensor. Two types of sample have been prepared, one with typical HF anodizing solution and the other with the presence of peroxide (H₂O₂) in the solution. The Fourier transform infrared (FT-IR) measurements on the PS layer on the Si substrate showed that the typical PS surface is characterized by chemical species like Si–H and Si–O. Samples anodized with peroxide based (H₂O₂) solution showed a PS structure with higher porosity (～80%) and better surface passivation (higher concentration of Si–O and Si–H species) compared to those not treated with peroxide. Peroxide based PS sample fabricated as an H₂ gas sensor showed better electrical (I–V) sensitivity compared to those without peroxide, which has been associated with good surface passivation. Surface passivation in peroxide based PS is also maintained at higher temperatures (100 °C).     

Structural and photoelectrical characteristics of Si/6H-SiC heterojunctions prepared by hot-wall chemical vapor deposition

Based on a potential application for the Si/SiC heterojunction to realize light control of SiC devices, structures and electrical properties of boron-doped silicon layer deposited on the n-type 6H-SiC substrate by hot-wall chemical vapor deposition were investigated in this paper.X-ray diffraction analysis and scanning electronic microscopy were used to characterize the crystal structure and morphology of the deposited silicon layer. Results of I–V and C–V measurements indicated that the heterojunction was abrupt manifesting obvious p–n junction properties. During the I–V measurement, the Si/SiC heterojunction developed a remarkable photovoltaic effect under illumination condition.     

Photoelectrochemical Water Oxidation by GaAs Nanowire Arrays Protected with Atomic Layer Deposited NiO<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> Electrocatalysts

Photoelectrochemical (PEC) hydrogen production makes possible the direct conversion of solar energy into chemical fuel. In this work, PEC photoanodes consisting of GaAs nanowire (NW) arrays were fabricated, characterized, and then demonstrated for the oxygen evolution reaction (OER). Uniform and periodic GaAs nanowire arrays were grown on a heavily n-doped GaAs substrates by metal–organic chemical vapor deposition selective area growth. The nanowire arrays were characterized using cyclic voltammetry and impedance spectroscopy in a non-aqueous electrochemical system using ferrocene/ferrocenium (Fc/Fc+) as a redox couple, and a maximum oxidation photocurrent of 11.1 mA/cm² was measured. GaAs NW arrays with a 36 nm layer of nickel oxide (NiO _x ) synthesized by atomic layer deposition were then used as photoanodes to drive the OER. In addition to acting as an electrocatalyst, the NiO _x layer served to protect the GaAs NWs from oxidative corrosion. Using this strategy, GaAs NW photoanodes were successfully used for the oxygen evolution reaction. This is the first demonstration of GaAs NW arrays for effective OER, and the fabrication and protection strategy developed in this work can be extended to study any other nanostructured semiconductor materials systems for electrochemical solar energy conversion.