一种高性能的亚阈值CMOS电压基准

基于0.18 μm CMOS工艺设计了一种高性能的亚阈值CMOS电压基准。提出了一个电压减法电路,将两个具有不同阈值电压且工作在亚阈值区晶体管的栅源电压差作为电压基准输出。所提出的电压减法电路还可以很好地消除电源电压变化对输出基准的影响。后仿仿真结果表明,所设计的电压基准在0.55~1.8 V电源电压范围内,线性灵敏度为0.053%/V~0.121%/V;在-20 ℃~80 ℃范围内,温度系数为9.5×10-6/℃~3.49×10-5/℃;在tt工艺角、0.55 V电源电压下,电源抑制比为-65 dB@100 Hz,功耗为3.7 nW。芯片面积为0.008 2 mm²。该电路适用于能量采集、无线传感器等低功耗应用。     

超低功耗亚阈值CMOS电压基准电路

采用SMIC 0.18μm CMOS工艺,设计了一种基于亚阈值MOS管的超低功耗、低温度系数的全CMOS电压基准电路。电路可在0.6~5V的工作电压范围内工作,当工作电压为1V时,功耗为1.12nW。在-20℃~80℃温度范围内,电路的最低温度系数为2.7×10-6/℃。在无片外滤波电容的情况下,电路的电源抑制比在100Hz和10MHz时分别为-56dB和-45dB。     

一种新型的CMOS亚阈值低功耗基准电压源

利用工作于亚阈值的NMOS器件,产生两个负温度系数的电压源,然后将两个电压源作差,产生稳定的基准电压输出.整体电路采用HJTCl80 nrn标准CM（）S工艺实现.仿真结果表明,基准源输出电压为220 mV,在一25℃到100℃的温度范围内的温度系数为68×10^-6/ C.电路的最小供电电压可低至O.7 V,在供电电压O.7～4V范围内的线性调整率为1.5 mV/V.无滤波电容时,1 kHz的电源抑制比为-56 dB室温下,1.O V电压供电时,电路总体功耗为3.7μW.版图设计后的芯片核心面积为O.02 mm².本文设计的电压源适用于低电压低功耗的条件.     

一种低失调低温漂基准电压源设计

基于传统的Brokaw结构带隙基准源进行改进,采用无运放的Brokaw结构基准源,避免运算放大器带来的输入失调电压的影响,提高基准电压精度。针对不同工艺角下基准温度特性曲线零温度系数点变化导致温度系数变差的问题,设计了一种分段线性温度补偿与电阻修调结合的补偿修调方案,对基准输出进行温度补偿的同时修调电压精度。相比于传统分段线性补偿法,该方案避免了在其他工艺角下分段补偿时出现的补偿不足或补偿过度的情况,实现了基准电压源输出在器件全工艺角组合下的低温度系数和高精度。电路基于TSMC 0.18 μm BCD工艺设计。仿真结果表明,该电路在5 V电源电压下输出电压为1.201 V,输出失调电压为3.3 mV。在全工艺角下,-40 ℃～+125 ℃温度范围内,基准电压温度系数最大为7.48×10-6/℃,输出电压为1.201(1±0.16%) V。     

一种基于横向PNP管的低失调CMOS带隙基准源

基于横向寄生PNP管,提出了一种新颖结构的低失调CMOS带隙基准源。该带隙能够降低运放失调电压和镜像电流对基准电压的影响,提高带隙抗工艺失调的能力。仿真结果表明,基准电压为1.228 0V,在-40℃~125℃,典型偏差小于2.7mV,温度系数为13.9ppm/℃。该带隙具有较好的工艺稳定性,在各工艺角情况下,失调电压小于±25.3mV,比传统带隙相对精度提高了3.3倍。最后,基于0.35μm CMOS工艺实现了该电压基准源。     

基于CMOS的低功耗基准电路的设计

基于带隙基准的原理,采用0.6μm、N阱CMOS工艺,文章设计了一种工作在亚阈值区的用于锂离子和锂聚合物电池充电保护芯片的低功耗基准电路。Hspice仿真结果表明:基准电压为1.068V,电源电压由1.8V到8V变化,电路最大消耗电流小于0.15μA;温度由-40℃到80℃变化,其温度系数约为±10ppm/℃。整个充电保护芯片测试结果,其功耗小于0.6μW。     

PVT恒定高精度亚阈值CMOS电压基准源

提出一种基于SMIC 65 nm标准CMOS工艺库的高精度电压参考源电路。对3种不同类型偏置于亚阈值区的NMOSFET进行了讨论,采用无电阻温度补偿对温度进行高阶补偿,可以减小对工艺、电压、温度的敏感性。仿真结果表明:在不同工艺角下,电源电压、温度使基准电压Vref的变化仅为±1.36%。电压参考源的温度系数大约为4.5×10-6℃-1,电源线性调制率为2.1%m V·V-1,最小工作电压仅为0.56 V。     

一种高性能的亚阈值基准电压源设计

本文给出了一种基于亚阈值MOS特性的基准电压源.通过使用线性区工作的MOS管代替传统电阻来消除掉迁移率和电流的温度影响,拓宽了温度范围,改善了性能.采用0.5μmCMOS工艺进行仿真.结果表明电路能在2.5～8V范围内工作,线性调整率为0.3mV/V.在3.3V工作电压下,输出基准在-55℃到150℃温度范围内温度系数为7.3ppm/℃,静态功耗为13.8μW,1kHz下电源抑制比为-53dB.该基准电压源的设计能满足宽温度范围、低温漂、低功耗和高电源抑制比的要求.     

一种带有失调消除电路的带隙基准设计

设计一种带有消除失调电压的带隙基准源。采用NEC的0.35μm 2P2M标准CMOS工艺,在Cadence Spectre环境下进行设计和仿真。该电路比传统的带隙基准电路具有更高的精度和稳定性。带隙基准的输出电压为1.274 V,在3~6 V的电源电压范围内基准电压随输入电压的最大偏移为0.4 m V;在-55~125℃的温度范围内,基准电压随温度的变化为4 m V,产生的偏置电流基本上不受电源电压的影响,而与温度成线性关系。该电路以增加芯片功耗和面积为代价,消除失调电压对电路的影响。基准电压电源抑制比可达到85 d B。     

低静态电流CMOS电压基准源设计

为了实现低功耗,尤其是低的静态功耗,在传统的带隙基准基础上设计的低静态电流CMOS基准源,是利用CMOS晶体管工作在弱反型区饱和漏电流随电压呈指数关系的原理实现的.在保证低温度系数18.9×10-6℃和高精度的同时,实现了低的静态电流.仿真的结果显示其输出基准电压是1.109 V,工作电压3 V时,消耗功耗为1.2 μW.     

A low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs

This paper describes a CMOS voltage reference using only resistors and transistors working in weak inversion,without the need for any bipolar transistors.The voltage reference is designed and fabricated by a 0.18μm CMOS process.The experimental results show that the proposed voltage reference has a temperature coefficient of 370 ppm/℃at a 0.8 V supply voltage over the temperature range of-35 to 85℃and a 0.1%variation in supply voltage from 0.8 to 3 V.Furthermore,the supply current is only 1.5μA at 0.8 V supply voltage.     

一种工作在亚阈值区的低电压低功耗基准电压电路

本文提出了一种不使用三极管而只使用工作在亚阈值区的晶体管和电阻的电压基准。使用0.18um工艺进行流片以及测试的结果表明：本文所设计的电压基准可在0.8V的低电压下工作,在温度从-35˚C到85˚C的范围内,温度系数为370ppm/˚C;电源电压从0.8V到3V的条件下,电压偏差小于0.1%。而且在电源电压为0.8V的条件下,整个芯片的功耗只有1.5uA。     

A high-order curvature compensation technique for bandgap voltage reference using subthreshold MOSFETs

A bandgap voltage reference with high-order curvature compensation is presented in this study. It exploits subtraction and derivative equalisation of currents generated from two complementary NMOS and PMOS bandgap references (BGRs) using subthreshold MOSFETs. By equating the derivative with respect to temperature of the two currents, generated by the complementary bandgaps, and subtracting these currents, an accurate high-order curvature compensation is achieved. To overcome problems due to the limited input common-mode range of opamps used in BGRs, a transimpedance amplifier with new accurate current compensation that tracks the temperature variation is proposed. This bandgap is implemented using the 0.18 μm CMOS process with a supply voltage as low as 0.7 V. At 0.8 V power supply and an output reference voltage of 386 mV, the proposed circuit achieves a temperature coefficient of 19 ppm/°C from 0 to 130°C. The power consumption is 119 μW and the power supply reduction ratio is 24 dB at 1 kHz.     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.     

一种极低功耗的CMOS带隙基准源

随着SoC在便携产品中应用的迅猛发展,低功耗技术变得越来越重要。本文采用了0.18um的标准CMOS工艺来,设计了一种无电阻、工作在亚阈值区的低功耗、小面积的CMOS电压基准源。这个带隙基准可以灵活运用于极低功耗的SoC系统中。这个电路的电源电流大约为150nA,可以在1.5V～3.3V之间的电源电压下工作,基准源的输出电压的线性度为44.4ppm/V。当电源电压为1.5V,室温下带隙基准电路的输出电压为1.1126V,100Hz频率下的电源抑制比为-66dB,当温度在-20℃与80℃之间变化时,输出电压的温度系数是55ppm/℃。整个带隙基准的芯片面积是0.011mm2。     

A sub 1 V high PSRR CMOS bandgap voltage reference

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst case over temperature range −40 to 140°C, 60 ppm/V of supply voltage dependence and 60 dB PSRR at 1 MHz without trimming or extra circuits for the curvature compensation. The entire circuit occupies 0.027 mm² of die area and consumes from a 1.2 V supply voltage at room temperature. Twenty chips are tested to show the robustness of the topology and the measurement results are compared with Monte Carlo simulation and analysis.     

A novel current reference based on subthreshold MOSFETs with high PSRR

A novel current reference based on subthreshold MOSFETs with high power supply rejection ratio (PSRR) is presented. The proposed circuit takes full advantages of the I-V transconductance characteristics of MOSFET operating in the subthreshold region and the enhancement pre-regulator with the high gain negative feedback loop for the current reference core circuit. The proposed circuit, designed with the SMIC 0.18 μm standard CMOS logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient of 2.5×10⁻⁴ μA/°C in the temperature range of −40 to 150 °C at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about −126 dB at dc frequency and remains −92 dB at the frequency higher 1 MHz. The proposed circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.     

无电阻低压低温漂的CMOS基准电压源

结合工作在亚阈值区、饱和区和线性区的MOS管,提出一种纯MOS结构的基准电压源,其结构能有效补偿MOS管的栽流子迁移率和亚闽值斜率的温度系数。基于SMIC0．13μm的CMOS工艺的仿真结果表明,在-5-90℃的范围内。输出电压的温度系数为5ppm／℃。在室温时,整个电路能在低到0．9V的电源电压下工作并消耗0．68μW的功耗。     

Novel high PSRR high-order temperature-compensated subthreshold MOS bandgap reference

Novel high power supply rejection ratio (PSRR) high-order temperature-compensated subthreshold metal-oxide-semiconductor (MOS) bandgap reference (BGR) is proposed in Semiconductor Manufacturing International Corporation (SMIC) 0.13 μm complementary MOS (CMOS) process. By adopting subthreshold MOS field-effect transistors (MOSFETs) and the piecewise-curvature temperature-compensated technique, the output reference voltage's temperature performance of the subthreshold MOS BGR is effectively improved. The subthreshold MOS BGR achieves high PSRR performance by adopting the technique of pre-regulator. Simulation results show that the temperature coefficient (TC) of the subthreshold MOS BGR is 1.38×10^?6/°C when temperature is changed from ?40 °C to 125 °C with a power supply voltage of 1.2 V. The subthreshold MOS BGR achieves the PSRR of ?104.54 dB, ?104.54 dB, ?104.5 dB, ?101.82 dB and ?79.92 dB at 10 Hz, 100 Hz, 1 kHz, 10 kHz and 100 kHz respectively.