带优先权的时间片多任务分配新算法

本文讨论了实时控制系统的几种常见多任务实时性分配算法的优缺点，并提出一种能满足多任务实时性分配的新算法一用带优先权的时间片分配多任务的算法。     

基于VxWorks的多任务程序设计及通信管理

为了满足系统各个任务对实时性的要求,需要实现各个任务的并行处理。针对VxWorks操作系统的多任务调度机制和任务通信方式进行了分析;采用基于时间片轮转调度实现多任务程序设计,可以动态改变各个任务期望运行的时间片;对各种通信方式和实现方法进行了比对,并给出了优化方案。上述设计方法实时性强,可靠性高,系统可扩展性良好,能够很好地满足工程需要。     

多域光网络中基于优先级的波长路由分配算法

本文提出一种在多域光网络中基于优先级的路由波长分配算法.算法设计旨在解决复杂网络拓扑下,多任务请求路由波长分配问题.本文首先根据复杂网络拓扑情况与任务请求状况,完成多域的划分,对跨域任务的最短路由进行路由分裂;其次依据域内与域间优先级设定策略,完成多任务请求优先级设定;按照优先级顺序,采用模糊优化波长分配算法完成波长分配.仿真结果表明本算法在处理复杂网络拓扑、多任务路由波长分配问题上效果明显,有效的降低了网络请求阻塞率,提高了光网络资源利用率.     

基于软件流水线的并行多源视频处理

针对多源、复杂视频处理存在的实时性低,资源占用率高的问题,提出了一种基于软件流水线并行处理多源视频的方法,具有降低视频处理应用的设计难度,优化计算资源使用,提高复杂算法多源视频处理的实时性的特点.首先基于多核CPU构建多任务管理系统,用于任务缓存及调度,并管理资源负载,在此基础上设计软件流水线.软件流水线的每一个stage将对于一帧视频图像的处理封装成任务的形式提交给多任务管理系统调度执行.最后,将软件流水线用于多源视频处理,并行处理6路视频,试验结果表明该方法能够有效提升多源、复杂视频处理的实时性,且在资源利用率,负载均衡等方面具有良好特性.     

一种基于VxWorks的高速实时数据记录系统的设计

本文针对大规模数据记录系统对嵌入式系统实现的实时性需求,设计了一种采用VxWorks操作系统的嵌入式实现方案,该方案采用模块化的设计架构,利用VxWorks灵活的多任务调度机制和任务间通信机制,建立了一种多任务间通信模型.通过对任务功能的合理划分和任务优先级的设置,该嵌入式系统克服了数据记录过程中数据丢失、数据覆盖的问题,提高了数据记录的实时性和可靠性要求.     

基于Vxworks的语音控制系统多任务调度算法的研究

研究了一种用于电力控制的基于Vxworks的语音控制系统的多任务调度算法,根据系统功能划分了任务及优先级,采用信号量通信方式,设计了时间片轮转和基于优先级抢占的混合调度算法,经仿真测试,算法运行效果稳定,任务切换时间达到毫秒级。     

一种基于QoS的多任务实时集群系统负载均衡算法

负载均衡算法是多任务实时集群系统的一个关键技术。在分析了常见的轮转式均衡调度算法和任务最少优先法的优缺点基础上,针对实时集群系统处理多类任务的特点,引入了加权负载率的概念来更准确地描述各分布式集群节点的负载状况。提出了通过任务QoS映射为负载权值的思想,并给出了一种改进的任务最少优先算法——加权负载率最小法,描述了以加权负载率表为核心的多任务均衡调度算法。最后,通过仿真验证了该算法明显优于前两种算法。     

水下传感器网络目标跟踪时的非短视比特优化分配算法

由于水下传感器网络(Underwater Sensor Network,USN)的能量、带宽有限,传输原始量测数据前需要进行量化处理。面向目标跟踪,在传输比特数据量的约束下,提出了非短视量化比特分配算法。首先,推导了量化量测下的条件后验克拉美罗下界,并将其设为优化目标,建立了比特分配优化模型。在此基础上,提出了一种双层近似动态规划的算法来实现比特分配的优化,在所设时间窗内利用第一层近似动态规划分配各个时刻的比特,并利用第二层近似动态规划在各分支上实现水下传感器节点的比特分配,进一步提升了计算效率。仿真结果表明,所提算法在满足实时性的要求下具有更稳定的跟踪性能。     

嵌入式实时操作系统μC/OS-Ⅱ在P89V51RD2中的移植

引言 自嵌入式系统开发以来，很长时间都采用前后台系统软件设计模式：主程序为一个无限循环，单任务顺序执行。通过设置一个或多个中断来处理异步事件。这种系统对于简单的应用是可以的，但对于实时性要求比较高的、处理任务较多的应用，就会暴露出实时性差、系统可靠性低、稳定性差等缺点。μC／OS—Ⅱ是一种基于优先级的抢占式多任务实时操作系统，包含了实时内核、任务管理、时间管理、任务间通信同步（信号量，邮箱，消息队列）和内存管理等功能。     

量子二分检索算法及其实现线路

考虑到量子比特与经典比特的本质区别,提出了一种量子二分检索算法.利用量子并行处理和量子置换操作,给出了量子二分检索算法的线路实现.通过实例表明,相比于经典二分法检索算法,本文提出的算法方案可以大大减少操作时序,降低整个算法的完成时间,对量子线路在"退相干"时间内完成量子信息处理具有重要的应用价值.     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

A stereo audio sigma-delta A/D-converter

A stereo sigma delta A/D-converter for audio applications is presented. In this converter, two identical cascaded fourth-order sigma-delta modulators and a sophisticated multistage linear-phase FIR decimation filter with oversampling ratio of 64 are implemented on the same die. The analog part is designed to operate at a low voltage with a low power consumption. Techniques to achieve simultaneously a high performance and a low power consumption are discussed in details. The minimum stopband attenuation of the decimator is more than 120 dB and the passband ripple of the overall converter is less than 0.0003 dB. The first decimation stage is a special tapped comb filter, whereas the remaining stages are realized without general multipliers by simultaneously implementing all the filter coefficients by using special bit-serial networks. For the integrated overall stereo converter, the power consumption and the signal-to-noise ratio are 180 mW and 97 dB (85 mW and 95 dB) for a 5 V (3 V) power supply. The circuit die area is only 4.7 mm×5.5 mm using a 1.2 μm double-poly BiCMOS process