时钟抖动和相位噪声对数据采集的影响

随着采样频率和A/D变换器位数的增加,时钟抖动和相位噪声对数据采集系统性能的影响更加显著.从相位噪声的双边带功率谱密度出发,详细分析了相位噪声和周期间抖动之间的联系,指出了相位噪声的不同频段对周期间抖动的影响,讨论了数据采集信噪比与时钟抖动和相位噪声之间的关系;并通过仿真给予定量的计算,对时钟源和数据采集系统的设计提供了一些建议;最后,利用某雷达数据采集系统进行实验,给出了相关实验结果.     

时钟抖动对ADC性能的影响分析

时钟的孔径抖动是影响ADC动态性能的重要因素。分析了时钟抖动对ADC动态性能的影响,并对时钟抖动与相位噪声的关系进行了论述,给出了时钟抖动与相位噪声之间的换算方法,对于正确选择ADC的采样时钟具有指导意义。     

一种应用于阵列TDC的低抖动锁相环设计

传统的PLL（Phase Locked Loop）电路受限于环路参数的选定,其相位噪声与抖动特性已经难以满足大阵列、高精度TDC（Time-to-Digital Converter）的应用需求.本文致力于PLL环路带宽的优化选取,采取TSMC 0.35μm CMOS工艺实现了一款应用于TDC的具有低抖动、低噪声特性的锁相环（Phase Locked Loop,PLL）电路,芯片面积约为0.745mm×0.368mm.实际测试结果表明,在外部信号源输入15.625MHz时钟信号的条件下,PLL输出频率可锁定在250.0007MHz,频率偏差为0.7kHz,输出时钟占空比为51.59%,相位噪声为114.66dBc/Hz@1MHz,均方根抖动为4.3ps,峰峰值抖动为32.2ps.锁相环的相位噪声显著降低,输出时钟的抖动特性明显优化,可满足高精度阵列TDC的应用需要.     

基于时钟抖动跟踪的PLL工作稳定性监测

针对复杂设备中PLL工作稳定性监测问题,建立了一种基于时钟抖动跟踪技术的PLL监测模型.采用迟延系统保证输入时钟与PLL时钟同相,消除了输入时钟抖动对PLL抖动判断的影响,利用先验知识序列消除了判断序列中确定分量,确保模型判断序列中只有PLL输出时钟抖动引起的噪声分量,利用计数器对噪声分量进行采集周期内统计,可以判定P...     

时钟抖动对A/D变换器采样性能的影响

时钟抖动时是影响ADC性能指标的重要因素。本文首先给出了时钟抖动和相位噪声的定义,并分析了二者之间的换算关系;然后给出了时钟抖动对A/D变换器的影响;最后结合某工程中的实测数据验证了时钟抖动对A/D变换器性能的影响。     

低抖动锁相环中压控振荡器的设计

压控振荡器(VC0)作为PLL系统中的关键模块,其相位噪声对PLL相位噪声和抖动产生决定性影响.在对PLl系统噪声及VCO相位噪声分析的基础上,基于CSMC 0.5μm CMOS工艺,设计了一款低相位噪声两级差分环形VCO.Spectre RF仿真结果表明,VCO频率调谐范围为524 MHz～1.1 GHZ,增益最大值Kvco为-636.7 MHz/V,900 MHz下VCO相位噪声为-116.2dBc/Hz@1 MHz,功耗为21.2 mW.系统仿真结果表明,VCO相位噪声对PLL抖动的贡献小于1 ps.     

集成电路

可利用GPS信号进行同步的时钟ICAD9548内置一个数字PLL,能对1ppsGPS信号进行上变频,同时可将与外部参考相关的输入时间抖动或相位噪声降低至300fs。时钟分配部分提供四     

高性能单频和双频晶体振荡器模块

9款NBXxxxx系列基于锁相环的PureEdge时钟模块可替代晶体振荡器,适用于高速网络、电信和高端计算应用。该系列使用高Q值基础模型晶体和模拟PLL乘法器来提供单频或双频、超低抖动和相位噪声的低压正射极耦合逻辑（LVPECL）／共模逻辑（CML）差分输出。NBXSxxx（单频）／NBXDxxx（双频）系列的性能包括极佳的长期时域抖动性能和10MHz优异的-163dBc／Hz器件本底噪声,     

采样时钟抖动、相噪与输出SNR关系研究

射频数字化技术是软件无线电接收机理想实现形式,并随着高速、高分辨ADC技术的飞速发展在雷达、通信、电子战领域得到了广泛的应用。由于采样时钟对射频信号的卷积效应和采样折叠效应,采样时钟的性能将直接决定输出信号的SNR。文章对射频数字化采样时钟抖动、相位噪声与输出SNR关系进行了研究、仿真和试验,给出了不同应用场合和需求下时钟对抖动、相位噪声的要求,可用于指导射频数字化采样时钟的设计。     

高速ADC的低抖动时钟设计

本文首先分析了采样时钟抖动对ADC信噪比性能的影响,然后指出产生时种抖动的原因,最后给出了两种实用的低抖动采样时钟产生方案:基于低相位噪声VCO(压控振荡器)的可变采样时钟的产生及基于极低相位噪声温度补偿晶振的非可变采样时钟的产生。     

A performance analysis of an all-optical clock extraction circuitbased on Fabry-Perot filter

A performance analysis of an optical clock extraction circuit based on a Fabry-Perot filter (FPF) is presented. Two analytical methods, time-domain and frequency-domain analysis, are developed in this paper. Time-domain analysis shows that there is no phase jitter in the extracted optical clock if the free spectral range (FSR) of the FPF is exactly equal to the signal clock frequency. Based on this, we obtain an analytical expression for root mean square (rms) amplitude jitter of the extracted optical clock in time domain, in which we have taken the impacts of carrier frequency drift and carrier phase noise into account. When the FSR of the FPF deviates from the signal clock frequency, both phase jitter and amplitude jitter will occur in the extracted optical clock. In this situation, a more general frequency-domain method is developed to deal with the timing performance under the assumption that carrier phase noise is negligible. This method allows us to calculate both rms phase jitter and rms amplitude jitter of the extracted optical clock. Using the developed two methods, we present a detailed numerical investigation on the impacts of finesse of the FPF, carrier frequency drift, resonator detuning, carrier phase noise, and optical pulse chirp on the timing performance. Finally, the application of this circuit in multiwavelength clock recovery is discussed     

时钟抖动对中频线性调频采样及脉冲压缩影响的研究

时钟抖动是模数转换过程中影响信号信噪比的最主要因素之一。该文从时域连续信号角度出发,按照高斯随机过程模型,分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。结合量化噪声的影响,可定量计算影响信噪比各因素之间的关系。仿真结果表明适用于模数转换后所得离散数字信号信噪比计算。合成孔径雷达经过脉冲压缩得到图像,为了抑制旁瓣需要使用窗函数加权,分析了时钟抖动在加窗前后对脉冲压缩时峰值旁瓣比和积分旁瓣比的影响。最后讨论了一些减小时钟抖动的具体措施。     

用于星光III激光同步系统的低抖动时钟整形技术

针对参考时钟源高电平脉冲宽度窄(小于2 ns)和本底噪声大的问题,通过使用一种时钟低抖动整形技术方案,使参考时钟经过锁相整形后高电平脉冲宽度大于3 ns、锁相相位时间抖动均方根(RMS)值小于5 ps。目前该方案已成功用于星光III激光装置的联机实验,情况良好,对其他类似需要精密时钟的装置具有极大的借鉴意义。     

Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling

This paper investigates nature and effects of jitter on the clock edge that triggers the sample/hold used in direct-sampling and IF-sampling receiver architectures. The impact of the aperture uncertainty is theoretically discussed, simulated, and measured in the case of the high-frequency front-end of a 16-bit 65 MS/s analog-digital converter. Both characterizations of the phenomenon are considered: in the frequency domain [single-sideband to carrier ratio (SSCR), or phase noise] and in the time domain (aperture jitter). Theory and measurements are provided for the classic Leeson model, the spectrum caused by flicker noise, and the practically most relevant white noise case. In each instance, not only the degradation of the overall signal-to-noise ratio in presence of a large blocker is quantified; but a closed-form formula is introduced that rigorously quantifies the ldquospotrdquo scaling factor between the SSCR of the clock and the one of the sampled signal, for every offset frequency .     

Analyzing the effect of the phase-jitter in the operation of second order phase-locked loops

Phase-locked loops (PLLs) are designed to extract timing signals in telecommunication networks. Noise, cross-talk, inter-symbol interference, quantization noise, and signal distortion are responsible for oscillations in the time between two successive transitions of the clock or data signal. It appears as an accidental phase modulation superposed to the original signal. This phenomenon is called timing jitter and affects the integrity of the data recovering process and, as a consequence, the error bit rate is increased. This problem has been studied by treating the jitter as a band limited noise process and tolerance masks for the jitter amplitude and frequency are recommended for several network architectures. Here, we develop a simple model with the continuous phase deviations of the clock signals considered as periodic signals in the band of the real disturbances. Comparisons with the stochastic approach are presented.     

Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.     

Jitter and phase noise in ring oscillators

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed     

时钟抖动对射频脉宽调制性能的影响分析

在全数字发信机系统中,射频脉宽调制(RF-PWM)将基带调制信号的幅度与相位信息编码为输出脉冲的宽度和位置。由于数字信号处理器件的非理想特性,其时钟信号的上升沿和下降沿存在抖动误差,影响RF-PWM的输出信号质量。基于3种RF-PWM实现方案,本文通过公式推导确定了时钟抖动引入的非线性失真项,并给出了时钟抖动影响下不同方案输出脉冲信号底噪的数学解析式。最后利用Matlab软件,对不同方案在时钟抖动条件下的基波、奇次谐波和底噪进行仿真验证,结果证明理论推导正确;同时对信号的矢量幅度误差(EVM)和邻信道功率比(ACPR)进行仿真,分析出时钟抖动对信号带内外性能的影响。结果表明,时钟抖动引入的非线性失真主要体现为底噪的抬高;不同RF-PWM实现方案时钟抖动的影响特性各有不同,其中五电平方案对时钟抖动影响具有抑制效果,且随时间分辨力的增大而增大。     

DDS线性调频信号时钟抖动误差分析

直接数字频率合成(DDS)是产生线性调频(LFM)信号常用方法,时钟抖动是影响其信号质量的因素之一.从时域出发,建立了由时钟抖动引起的DDS输出误差模型,推导出了抖动引起的LFM信号信噪比理论预测公式.分析指出随着时钟频率的提高,时钟抖动对信噪比的影响更加明显;当时钟抖动低于10 ps时,信噪比对时钟抖动的变化更为敏感.针对给定的信噪比要求和确知的LFM信号,给出了时钟抖动的限定公式,设计者可据此选择恰当的时钟源.最后,通过实验验证了理论推导的正确性.