Simple technique using local CMFB to enhance slew rate and bandwidth of one-stage CMOS op-amps

A simple modification to a one-stage op-amp for operation as a class AB amplifier leads to significant slew rate and bandwidth enhancement with essentially equal silicon area and static power dissipation requirements. Experimental results of a prototype in 0.5 /spl mu/m CMOS verify SR and bandwidth enhancement factors of almost one order of magnitude.     

High current efficiency single-stage bulk-driven subthreshold-biased class-AB OTAs with enhanced transconductance and slew rate for large capacitive loads

This paper introduces two high-performance single-stage bulk-driven (BD) operational transconductance amplifiers (OTA) in weak-inversion with rail-to-rail input and output voltage ranges suited for the excessively low-voltage of 0.5 V supply. The strategy depends on adopting a modified bulk-driven non-tailed input core to achieve high input core transconductance with a minimum power supply and an enhanced input common-mode range. Moreover, a partial positive feedback loop provides an overall improved DC gain and effective transconductance further. The input core of OTA1, named composite class-AB OTA, comprises two combined non-tailed differential pairs as composite differential pairs. The proposed OTA2, named composite super class-AB BD-OTA, exploits a matched bulk-input Flipped voltage follower (FVF) pair to adaptively bias the input core used in the composite class-AB BD OTA. As a result, a significant increase in large-signal input current to the output side due to super class-AB behavior improves the slew rate. The post-layout simulation results using the Cadence Spectre simulator with UMC 0.18 µm process technology confirm that the proposed OTAs have improved small-signal and large-signal performances over the conventional OTA driving a high capacitive load of 5 nF. The proposed composite class-AB and super class-AB BD OTA deliver 2.29 times, and 3.77 times open-loop DC gain, 10.6 times, and 117 times unity-gain bandwidth with 2 times, and 12.03 times slew rate at the expense of almost 0.52 times and 1.21 times power consumed over conventional counterpart, respectively.

     

A constant slew rate Ethernet line driver

An analog bias circuit consisting of two transistors, three current sources, and one resistor facilitates the design of an Ethernet line driver. The rise time is insensitive to process variations and temperature variations, Rise-time accuracy is 223 ppm/°C over a temperature range of 140°C. This line driver has been fabricated in 0.35-μm CMOS     

A single-stage operational amplifier with enhanced transconductance and slew rate for switched-capacitor circuits

The DVB-T2 standard for digital terrestrial broadcasting supports the use of quadrature amplitude modulation constellations where the constellation points are rotated in the I–Q plane. This combined with a cyclic delay of the Q component provides improved performance in some fading channels. The complexity of the optimal demapping process for rotated constellations is however significantly higher than for non-rotated constellations. This makes the DVB-T2 demapper one of the most computationally complex parts of a receiver. In this article, we examine possible simplifications of the demapping process suitable for implementation on a general purpose computer containing a modern graphics processing unit (GPU). Furthermore, we measure the performance in terms of throughput, as well as accuracy, of the implemented algorithms. The implementations are designed to interface efficiently to a previously implemented real-time capable GPU-based low-density parity-check channel decoder.     

A wide-band, low-power, high slew rate voltage-feedback operationalamplifier

A wide-band low-power voltage-feedback operational amplifier on a 3 GHz, 40 V complementary bipolar technology is described. The class AB input stage takes advantage of some current-boost transistors which enhance and linearize the slew-rate during large-signal operation without increasing the power consumption. The triple-buffered output stage provides 100 mA of load current maintaining good linearity. Since the circuit design and technology development were concurrent, several different circuits were stepped into one wafer to fully characterize the process and identify the best product candidates. The low-current version of this chip has a quiescent current of 2.5 mA, 2000 V/μs slew rate and gain bandwidth of 110 MHz. The medium-current version draws only 6.5 mA of current at the same supply voltage while the slew rate increases to 3500 V/μs and bandwidth to 210 MHz. Both parts are operational from +/-2.75 V to +/-18 V supply range. Die size is 51 mils by 76 mils on a poly-emitter CB process     

An accurate analysis of slew rate for two-stage CMOS opamps

This brief presents a time-domain model for the slew rate of CMOS two-stage Miller compensated operational transconductance amplifiers. The effects of both the first- and second-stage currents are considered in this model and a simple analytical expression is given in terms of the compensation and load capacitors, output voltage change, and device sizes. HSPICE simulation results are provided to show the validity of the proposed model using a 0.25-/spl mu/m CMOS technology.     

一种基于概率解释的新型互连线时延Slew模型

基于概率解释的互连线时延模型具有效率高,实现简单,估计准确等特点,在亚100纳米工艺IC设计及验证中具有较好的应用前景.基于概率解释的互连线时延模型往往需要大量的查表计算,对效率及计算精度都存在一定的影响,而且有些模型不能进行Slew的估计.本文提出了一种基于BS统计分布的互连线时延模型,完全避免了查表运算而且可直接用于Slew估计.90纳米工艺TCAD仿真实验结果表明,该模型在效率、精度、实现难易程度等方面具有一定的优势,对亚100纳米VLSI静态时序分析及相关EDA工具开发也有一定的参考价值.     

A novel switching architecture for ATM networks

It is known that the flexibility and capacity of asynchronous transfer mode (ATM) networks can meet the bandwidth requirements of multimedia applications. In ATM networks, switching is one of the major bottlenecks of end-to-end communication. We propose using a multiple partitionable circular bus network (MPCBN) as an ATM switch. Connection requests are first transformed into a graph where vertices and edges represent connection requests and conflicts among connection requests, respectively. We then use a graph traversal algorithm to select a maximal set of requests for execution in physically partitioned buses. An approach of using finite projective planes is then used to reduce the number of switch points from O(N²) to O(N √N), where N is the number of ports of a switch. A performance evaluation for both uniform and bursty data sources shows that the approach of using finite projective planes to reduce the number of switch points results in a small increase of cell loss probability     

A novel algorithm and architecture for adaptive digital beamforming

A novel algorithm and architecture are described which have specific application to high performance, digital, adaptive beamforming. It is shown how a simple, linearly constrained adaptive combiner forms the basis for a wide range of adaptive antenna subsystems. The function of such an adaptive combiner is formulated as a recursive least squares minimization operation and the corresponding weight vector is obtained by means of theQ-Rdecomposition algorithm using Givens rotations. An efficient pipelined architecture to implement this algorithm is also described. It takes the form of a triangular systolic/wavefront array and has many desirable features for very large scale integration (VLSI) system design.     

A novel and efficient routing architecture for multi-FPGA systems

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and field-programmable interconnect devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed, and previous research has shown that the partial crossbar is one of the best existing architectures. In this paper, we propose a new routing architecture, called the hybrid complete-graph and partial-crossbar (HCGP) which has superior speed and cost compared to a partial crossbar. The new architecture uses both hard-wired and programmable connections between the FPGAs. We compare the performance and cost of the HCGP and partial crossbar architectures experimentally, by mapping a set of 15 large benchmark circuits into each architecture. A customized set of partitioning and interchip routing tools were developed, with particular attention paid to architecture-appropriate interchip routing algorithms. We show that the cost of the partial crossbar (as measured by the number of pins on all FPGAs and FPIDs required to fit a design), is on average 20% more than the new HCGP architecture and as much as 25% more. Furthermore, the critical path delay for designs implemented on the partial crossbar were on average 20% more than the HCGP architecture and up to 43% more. Using our experimental approach, we also explore a key architecture parameter associated with the HCGP architecture-the proportion of hard-wired connections versus programmable connections-to determine its best value     

新型四次谐波混频电路

本文介绍了一种适用于高次谐波混频的电路原理图,基于空闲频率相位抵消理论,该混频电路结构可以避免复杂的空闲频率回收电路设计,同时能获得很高的端口隔离度。基于该结构,设计了新型的Ka波段四次谐波混频器,该混频器在38.4 GHz测得最小变频损耗 8.3 dB,在34-39 GHz 变频损耗小于10.3dB, LO-IF、RF-LO、 RF-IF 端口隔离度分别优于30.7 dB、 22.9dB、46.5dB。     

A novel kinematic architecture for portable hand exoskeletons

Basing on strict requirements of portability, low cost and modularity, an assistive device for hand-opening impairment, characterized by an innovative mechanism, has been developed and tested by the authors. This robotic orthosis is designed to be a low-cost and portable hand exoskeleton to assist people with hand-opening impairment in their everyday lives. The mechanism has been especially studied for this kind of applications and presents some interesting features in terms of limited encumbrances and costs. Concerning the hand-opening impairment, the authors have also developed a methodology which, starting from the geometrical characteristics of the patient’s hand, properly defines the novel kinematic mechanism that better fits the finger trajectories. The authors have tested and validated the proposed approach by building a functional Hand Exoskeleton System (HES) prototype. The preliminary testing phase of the prototype with a single subject is concluded; currently, a group of subjects is testing the proposed HES methodology in collaboration with a rehabilitation center.     

Embedded capacitor multiplier gain boosting compensation for large-capacitive-load three-stage amplifier with slew rate enhancement

An embedded capacitor multiplier gain boosting compensation (ECMGBC) technique with slew rate enhancement circuit is presented in this paper for a three-stage amplifier. The ECMGBC technique pushes the non-dominant complex poles of the amplifier to high frequencies for gain-bandwidth product (GBW) extension under low quiescent current. In addition, the proposed slew rate enhancement circuit improves the transient responses of ECMGBC amplifier without any problem of oscillation. The ECMGBC amplifier has been designed and simulated in a 0.35-µm mixed signal CMOS process. From the post-simulation results, the amplifier driving a 1,000-pF capacitance achieves a 1-MHz GBW with a phase margin of 60° by consuming 13.5-µA quiescent current. The total compensation capacitance is only 1.2 pF. The transient responses are simulated when the amplifier is in unity-gain non-inverting configuration with a 0.6-V step input at a 2-V supply. The 1 % settling time is 1.1 µs for a 1,000-pF load capacitance. Compared with previously reported works, the ECMGBC amplifier achieves good figures of merit. Moreover, the ECMGBC amplifier obtains a very high ratio of load capacitance to total compensation capacitance.     

A novel architecture for queue management in the ATM network

The author presents four architecture designs for queue management in asynchronous transfer mode (ATM) networks and compares their implementation feasibility and hardware complexity. The author introduces the concept of assigning a departure sequence number to every cell in the queue so that the effect of long-burst traffic on other cells is avoided. A novel architecture to implement the queue management is proposed. It applies the concepts of fully distributed and highly parallel processing to schedule the cells' sending or discarding sequence. To support the architecture, a VLSI chip (called Sequencer), which contains about 150 K CMOS transistors, has been designed in a regular structure such that the queue size and the number of priority levels can grow flexibly     

A novel image rejection architecture for quadrature radio receivers

In radio communications, a bandpass-to-lowpass transformation is needed to demodulate the received signal down to baseband. One crucial question in this context is how to effectively attenuate the image band signal. For this purpose, inphase/quadrature (I/Q) signal processing is widely utilized in today's radio receivers. In this paper, a novel structure for obtaining an image-free baseband observation of the received bandpass signal is presented. The starting point is to approximate the needed 90/spl deg/ phase difference between the I and Q branch signals using a simple time delay of one quarter of the carrier cycle. For narrowband signals, this approach can be used directly to attenuate the inherent "self-image". By using an interference canceller-type of compensation technique, this concept is here generalized to cover also wideband multichannel signals. Furthermore, a closed-form expression to explicitly characterize the obtainable image attenuation is derived. Efficient implementation structures for digital radios utilizing periodically nonuniform subsampling are presented, and the validity of the proposed approach is further illustrated through simulation and design examples.     

A new family of CMOS inverter-based OTAs for biomedical and healthcare applications

This paper presents a new family of innovative operational transconductance amplifier (OTA) topologies based on CMOS inverter structures, with improved gain and energy-efficiency. This new family of OTA designs is suitable for biomedical and healthcare circuits and systems, due to the high energy-efficiency, improved gain and low level of noise contribution, when compared to the state-of-the-art in this field. In this paper, two fully-differential implementations are presented, a first one with a double CMOS branch biased by two pairs of voltage-combiners structures in both NMOS and PMOS configurations, and a second one with folded voltage-combiners specifically targeting low voltage applications, e.g., supplies below 1 V. The usage of voltage-combiners to bias the OTAs improves the gain and the gain-bandwidth product, therefore improving the energy-efficiency figure-of-merit. High values of figure-of-merit are achieved in both implementations, i.e., more than 1600 MHz × pF/mA and 2000 MHz × pF/mA, gain values above 53 dB and 50 dB under supply sources of 2 V and 0.7 V respectively. The folded voltage-combiners biased OTA is able to operate correctly under a voltage supply down to 0.7 V with proper DC biasing. The results are finally compared with state-of-the-art in this field and the potential of the circuits is fulfilled using a state-of-the-art layout-aware integrated-circuit optimization framework, AIDA, particularly relevant in order to overcome the device stacking problematic for lower voltages.