Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

一种新型隧穿场效应晶体管

提出了一种新型隧穿场效应晶体管(TFET)结构,该结构通过在常规TFET靠近器件栅氧化层一侧的漏-体结界面引入一薄层二氧化硅(隔离区),从而减小甚至阻断反向栅压情况下漏端到体端的带带隧穿(BTBT),减弱TFET的双极效应,实现大幅度降低器件泄漏电流的目的。利用TCAD仿真工具对基于部分耗尽绝缘体上硅(PDSOI)和全耗尽绝缘体上硅(FDSOI)的TFET和新型TFET结构进行了仿真与对比。仿真结果表明,当隔离区宽度为2 nm,高度大于10 nm时,可阻断PDSOI TFET的BTBT,其泄漏电流下降了4个数量级;而基于FDSOI的TFET无法彻底消除BTBT和双极效应,其泄漏电流下降了2个数量级。因此新型结构更适合于PDSOI TFET。     

电子阻挡层对UV LED芯片老化后反向漏电的影响

着重对紫外(UV)LED芯片的反向漏电进行研究,使用高Al组分的AlGaN材料作为LED外延结构中的电子阻挡层(EBL),旨在解决UV LED芯片在老化后的漏电问题。结果表明,高Al组分的AlGaN EBL凭借其足够高的势垒高度,可以有效降低电子泄漏水平,从而改善UV LED芯片在老化后的反向漏电问题。选取365~415 nm波段、量子阱禁带宽度为3.0~3.4 eV的外延片为研究对象,研究了EBL工艺对老化后芯片漏电性能的影响,得到AlGaN EBL的最佳Al组分为30%~40%,对应禁带宽度为4.0~4.3 eV。使用该方法制作的UV LED芯片在经过长时间老化后,其漏电流可以保持在1 nA以下,综合性能大幅提升。     

Improved Electrical Performance and Reliability of Poly-Si TFTs Fabricated by Drive-In Nickel-Induced Crystallization with Chemical Oxide Layer

Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been employed to fabricate low-temperature polycrystalline silicon thin-film transistors (TFTs). However, the Ni residues degrade the device performance. In this study, a new method for manufacturing MIC–TFTs using drive-in Ni-induced crystallization with a chemical oxide layer (DICC) is proposed. Compared with that of MIC–TFTs, the on/off current ratio (I _on/I _off) of DICC–TFTs was increased by a factor of 9.7 from 9.21 × 10⁴ to 8.94 × 10⁵. The leakage current (I _off) of DICC–TFTs was 4.06 pA/μm, which was much lower than that of the MIC–TFTs (19.20 pA/μm). DICC–TFTs also possess high immunity against hot-carrier stress and thereby exhibit good reliability.     

Using Phosphorus-Doped α-Si Gettering Layers to Improve NILC Poly-Si TFT Performance

Ni-metal-induced lateral crystallization (NILC) has been utilized to fabricate polycrystalline silicon (poly-Si) thin-film transistors (TFTs). However, the current crystallization technology often leads to trapped Ni and NiSi₂ precipitates, thus degrading device performance. In this study, phosphorus-doped amorphous silicon (p-α-Si) and chemical oxide (chem-SiO₂) films were used as Ni-gettering layers. After a gettering process, the Ni impurity within the NILC poly-Si film and the leakage current were both reduced, while the on/off current ratio was increased. This gettering process is compatible with NILC TFT processes and suitable for large-area NILC poly-Si films.     

SiC肖特基势垒二极管的反向特性

在n型4H-SiC衬底上的n型同质外延层的Si面制备了纵向肖特基势垒二极管(SBD),研究了场板、场限环及其复合结构等不同终端截止结构对于反向阻断电压与反向泄漏电流的影响。场板(FP)结构有利于提高反向阻断电压,减小反向泄漏电流。当场板长度从5μm变化到25μm,反向阻断电压随着场板长度的增加而增加。SiO2厚度对于反向阻断电压有重要的影响,当厚度为0.5μm,即大约为外延层厚度的1/20时,可以得到较大的反向阻断电压。当场限环的离子注入区域宽度从10μm变化到70μm,反向阻断电压也随之增加。FLR和FP复合结构对于改善反向阻断电压以及反向泄漏电流都有作用,同时反向阻断电压对于场板长度不再敏感。采用复合结构,在10μA反向泄漏电流下最高阻断电压达到1 300V。讨论了离子注入剂量对于反向阻断电压的影响,注入离子剂量和反向电压的关系表明SBD结构不同于传统PIN结构的要求。当采用大约为150%理想剂量的注入剂量时才可达到最高的反向阻断电压而不是其他报道的75%理想剂量,此时的注入剂量远高于PIN结构器件所需的注入剂量。     

Carrier Transport Mechanism and Band Offsets at the Interface of ZnS/<Emphasis Type="Italic">n</Emphasis>-Si (111) Heterojunctions Fabricated by Vacuum Thermal Evaporation

The electrical properties and band offset of ZnS/n-Si(111) heterojunctions with and without annealing were analyzed. The result showed that the rectifying characteristics of ZnS/n-Si(111) heterojunctions became better and the leakage current increased after annealing. This phenomenon is mostly due to the volatilization of S atoms of ZnS films and leads to defect levels appearing at the interface of the ZnS/n-Si(111) hetrojunctions. The valence band offset (ΔE _V) of the ZnS/n-Si(111) heterojunctions can be calculated to be ?0.7 ± 0.15 eV by means of photoelectron spectroscopy, indicating that the band offsets of ZnS/n-Si(111) heterojunctions show a type-II band alignment.     

电流增益截止频率为236GHz的InAIN/GaN高频HEMT

研制了高电流增益截止频率(fT)的InAlN/GaN高电子迁移率晶体管(HEMT).采用金属有机化学气相沉积(MOCVD)再生长n+GaN非合金欧姆接触工艺将器件源漏间距缩小至600 nm,降低了源、漏寄生电阻,有利于改善器件的寄生效应;使用低压化学气相沉积(LPCVD)生长SiN作为栅下介质,降低了InAlN/GaN HEMT栅漏电;利用电子束光刻实现了栅长为50 nm的T型栅.此外,还讨论了寄生效应对器件fT的影响.测试结果表明,器件的栅漏电为3.8 μA/mm,饱和电流密度为2.5 A/mm,fT达到236 GHz.延时分析表明,器件的寄生延时为0.13 ps,在总延时中所占的比例为19％,优于合金欧姆接触工艺的结果.     

MIC薄膜多晶硅材料的动态镍吸除技术基本机理及其应用

首先阐述了MIC薄膜多晶硅材料动态镍吸杂技术的基本机理和主要工艺过程,然后以多晶硅薄膜晶体管(poly-Si TFT)为例研究了动态吸杂技术的应用.在研究金属诱导晶化多晶硅材料(MIC poly-Si)和以之为有源层的poly-Si TFT的过程中,发现在MIC多晶硅薄膜中含有部分残余的镍成份.而大部分存在于对撞晶界的残余镍成份会造成大量的缺陷,这将导致TFT器件性能乃至整个系统的稳定性和可靠性的降低.为了改善MIC薄膜及器件质量,我们采用磷硅玻璃(PSG)动态镍吸杂技术,有效地吸除镍,降低多晶硅中镍的残留量,改善对撞晶界的缺陷密度,降低用之制备TFT的漏电流.该技术工艺过程简单,处理成本低,适合于大批量的工业化生产,有望成为制备高稳定性微电子器件与电路系统的必需工艺技术.     

热丝CVD法沉积超薄α-Si∶H钝化膜

采用热丝化学气相沉积法在n型直拉单晶硅圆片表面双面沉积厚度为10 nm的本征非晶硅(α-Si∶H)薄膜.利用光谱型椭偏测试仪和准稳态光电导法研究热丝电流、H2体积流量和热丝与衬底之间的距离对α-Si∶H薄膜结构和钝化效果的影响.结果表明,热丝电流为21.5～23.5 A时,钝化后硅片的少子寿命随着热丝电流的增加呈现先增加后降低的趋势,热丝电流为23.0A时,钝化效果最好;H2体积流量为5～ 20 cm3/min时,少子寿命随着H2体积流量的增加呈现先增加后降低的规律,体积流量为15 cm3/min时,钝化效果最好;热丝与衬底间距为4～5 cm时,随着间距的增加,薄膜的结构由晶化向非晶化转变,在间距为4.5 cm时硅片的钝化效果达到最优.     

Transport properties and photosensitivity of metal/porous-silicon/c-Si structures

The current-voltage characteristics, photosensitivity, and impedance of p-type Al/porous-silicon/c-Si structures with 0.2 to 6-μm-thick porous layers of 80% porosity are studied. It is shown that at reverse and small forward bias voltages the current is determined by the potential barrier of the c-Si substrate at the isotypic porous-silicon/c-Si heterojunction. The photosensitivity is determined by the absorption of light in the c-Si substrate. The potential barrier of the metal/porous-silicon contact does not influence the photosensitivity or the currentvoltage characteristics of the structures. The experimental plots of the dependence of the impedance on applied forward bias, thickness of porous silicon layer, and frequency agree well with the theoretical dependences, if an equivalent circuit including two RC circuits connected in series and comprised of the resistance and geometric capacitance of the porous silicon layer and the resistance and capacitance of the potential barrier of the c-Si substrate is used. Fiz. Tekh. Poluprovodn. 33, 211–214 (February 1999)     

Cadmium sulfide passivation of InGaAs/InP mesa p-i-n photodiodes

A cadmium sulfide (CdS) passivation process was demonstrated for the first time on InGaAs/InP p-i-n mesa photodetectors. The passivated devices produced lower reverse bias leakage currents in comparison to devices that received only a thermally deposited SiO₂ film. The subsequent deposition of SiO₂ on the passivated devices produced virtually no change to the aforementioned leakage currents even after undergoing a 3-h, 300°C thermal treatment. In contrast, similar SiO₂ capped devices, fabricated without the CdS passivating layer, show a large increase in leakage current when subjected to the same thermal cycle. Leakage current versus mesa diameter measurements suggest these results are due to reduce surface recombination at the exposed mesa sidewall. X-ray photoelectron spectroscopy (XPS) results indicate the S:Cd ratio of these films to be 0.77.     

A mechanism of charge transport in electroluminescent structures consisting of porous silicon and single-crystal silicon

Electroluminescent structures that emit in the visible region of the spectrum and are based on porous silicon (por-Si) formed on the p-Si substrate electrolytically using an internal current source are fabricated. The photoluminescent and electroluminescent properties, as well as the current-and capacitance-voltage characteristics of the structures are studied. Electroluminescence is observed only if the forward bias voltage is applied to the structure; the electroluminescence mechanism is based on the injection and is related to the radiative recombination of electrons and holes in quantum-dimensional Si nanocrystals. The injection of holes is controlled by the condition of their accumulation in the space-charge region of p-Si and by a comparatively low concentration of electronic states at the por-Si/p-Si interface. The charge transport in por-Si is caused by the direct tunneling of charge carriers between the quantum-mechanical levels, which is ensured by an appreciable number of quantum-dimensional Si nanocrystals. The leakage currents are low as a result of a small variance in the sizes of Si nanocrystals and the absence of comparatively large nanocrystals.     

Controlling charge balance using non-conjugated polymer interlayer in quantum dot light-emitting diodes

The balance of electron–hole charge carriers in quantum dot (QD) light-emitting diodes (QLEDs) is an important factor to achieve high efficiency. However, poor interfacial properties between QDs and their adjacent layers are likely to deteriorate the electron–hole charge balance, resulting in the poor performance of a QLED. In this paper, we report an enhanced efficiency in red-emitting inverted QLEDs by modifying the interface properties between QDs and ZnO electron transport layer (ETL) using a thin layer of non-conjugated polymer, poly(4-vinylpyridine) (PVPy). Based on the precise control of the electrical properties with PVPy, the maximum efficiency of the QLED is enhanced by 30% compared to the device without a PVPy layer. In particular, the efficiency at low current density region is significantly increased. We investigate the effect of the PVPy interlayer on the performance of QLEDs and find that this thin layer not only shifts the energy levels of the underlying ZnO ETL, but also effectively blocks the leakage current at the ETL/QD interface.     

a-SiOx:H passivation layers for Cz-Si wafer deposited by hot wire chemical vapor deposition

In order to get the high photoelectric conversion efficiency a-Si:H/c-Si solar cells, high quality intrinsic hydrogenated passivation layer between the a-Si:H emitter layer and the c-Si wafer is necessary. In this work, hot wire chemical vapor deposition (HWCVD) is used to deposite intrinsic oxygen-doped hydrogenated amorphous silicon (a-SiO_x:H) and hydrogenated amorphous silicon (a-Si:H) films as the intrinsic passivation layer for a-Si:H/c-Si solar cells. The passivation effect of the films on the c-Si surface is shown by the effective lifetime of the samples that bifacial covered by the films with same deposition parameters, tested by QSSPC method. The imaginary part of dielectric constant (ε₂) and bonds structure of the layers are analyzed by Spectroscopic Ellipsometry(SE) and Fourier Transfom Infrared Spectroscopy(FTIR). It is concluded that: (1) HWCVD method can be used to make a-SiO_x:H films as the passivation layer for a-Si:H/c-Si cells and the oxidation of the filament can be overcome by optimizing the deposition parameters. In our experiments, the lowest surface recombination velocity of the c-Si wafer is 3.0 cm/s after a-SiO_x:H films passivation. (2) Oxygen-doping in the amorphous silicon layers can increase H content and the band-gap of films, similar as the phenomenon of the films deposited by PECVD.     

氢化非晶硅双极性场效应晶体管

本文着重研究了玻璃栅介质(GGI)氢化非晶硅双极性场效应晶体管(α-Si:HBFET)的转移特性,并比较了SiO_2和SiO_2/α-SiN_x:H栅介质α-Si:HFET的性质.业已发现:(1)硼掺杂和磷掺杂不仅可以人大地提高(GGI)α-Si:HBFET的电流驱动能力,而且可以大大地改善其双极对称性.(2)(GGI)未掺杂α-Si:HBFET可以用来构成静态特性良好的CMOS倒相器.(3)SiO_2栅介质α-Si:HFET具有典型的双极性,但是SiO_2/α-SiN_x:H栅介质α-Si:HFET则不是双极性的.     

基于AlN和GaN形核层的AlGaN/GaN HEMT外延材料和器件对比

使用金属有机物化学气相淀积(MOCVD)方法在蓝宝石衬底上分别采用AlN和GaN作为形核层生长了AlGaN/GaN高电子迁移率晶体管(HEMT)外延材料,并进行了器件制备和性能分析.通过原子力显微镜(AFM)、高分辨率X射线双晶衍射仪(HR-XRD)和二次离子质谱仪(SIMS)等仪器对两种样品进行了对比分析,结果表明采用AlN形核层的GaN外延材料具有更低的位错密度,且缓冲层中氧元素的拖尾现象得到有效地抑制.器件直流特性显示,与基于GaN形核层的器件相比,基于AlN形核层的器件泄漏电流低3个数量级.脉冲Ⅰ-Ⅴ测试发现基于GaN形核层的HEMT器件受缓冲层陷阱影响较大,而基于AlN形核层的HEMT器件缓冲层陷阱作用不明显.     

栅槽刻蚀工艺对增强型GaN HEMT器件性能的影响

基于凹槽栅增强型氮化镓高电子迁移率晶体管(GaN HEMT)研究了不同的栅槽刻蚀工艺对GaN器件性能的影响。在栅槽刻蚀方面,采用了一种感应耦合等离子体(ICP)干法刻蚀技术与高温热氧化湿法刻蚀技术相结合的两步法刻蚀技术,将AlGaN势垒层全部刻蚀掉,制备出了阈值电压超过3 V的增强型Al_2O_3/AlGaN/GaN MIS-HEMT器件。相比于传统的ICP干法刻蚀技术,两步法是一种低损伤的自停止刻蚀技术,易于控制且具有高度可重复性,能够获得更高质量的刻蚀界面,所制备的器件增强型GaN MIS-HEMT器件具有阈值电压回滞小、电流开关比(I_ON/I_OFF)高、栅极泄漏电流小、击穿电压高等特性。     

Study of the leakage current suppression for hybrid-Schottky/ohmic drain AlGaN/GaN HEMT

The leakage current suppression mechanism in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is investigated. It is known that leakage current can cause severe reliability problems for HEMT devices and conventional AlGaN/GaN HEMT devices suffer from detrimental off-state drain leakage current issues, especially under high off-state drain bias. Therefore, a leakage current suppression technique featuring hybrid-Schottky/ohmic-drain contact is discussed. Through the 2-zones leakage current suppression mechanism by the hybrid-Schottky/drain metal including the shielding effect of the rough ohmic-drain metal morphology and the drain side electric field modulation, AlGaN/GaN HEMT featuring this novel technique can significantly enhance the leakage current suppression capability and improve the breakdown voltage. An analytical method using loop-voltage-scanning is proposed to illustrate the optimization procedure of the hybrid-Schottky/ohmic drain metallization on leakage current suppression. Through the comparison of the loop leakage current hysteresis of conventional ohmic drain HEMT and hybrid-Schottky/ohmic drain, the leakage current suppression mechanism is verified through the leakage current considering surface acceptor-like trap charging/discharging model. Device featuring the hybrid-Schottky/ohmic drain technique shows an improvement in breakdown voltage from 450 V (with no Schottky drain metal) to 855 V with a total drift region length of 9 μm, indicating enhanced off-state reliability characteristics for the AlGaN/GaN HEMT devices.     

A novel insulated gate technology for ingaas high electron mobility transistors using silicon interlayer based passivation technique

A novel insulated gate technology for InGaAs high electron mobility transistors (HEMT) is described. It utilizes a silicon interface control layer (Si ICL)-based passivation structure. By applying an HF surface treatment, the technology becomes applicable to the air-exposed surfaces of InGaAs and InAlAs. The basic metal-insulator-semiconductor structures were fabricated and characterized in detail by x-ray photoelectron spectroscopy analysis and capacitance-voltage measurements. The interface has been shown to be essentially free from interface states. InGaAs insulated gate HEMTs (IGHEMT) were then success-fully fabricated. The fabricated recessed gate IGHEMTs have good gate control of the drain current with good pinch-off characteristics. A highest effective mobility of 2010 cm²/Vs was obtained. The devices show extremely low gate leakage currents below lnA/mm.