ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit

A substrate-triggered technique is proposed to improve the electrostatic discharge (ESD) robustness of a stacked-nMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of a stacked-nMOS device to ensure effective ESD protection for mixed-voltage I/O circuits. The proposed ESD protection circuit with substrate-triggered design for a 2.5-V/3.3-V-tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. The substrate-triggered circuit for a mixed-voltage I/O buffer to meet the desired circuit application in different CMOS processes can be easily adjusted by using HSPICE simulation. Experimental results have confirmed that the human- body-model (HBM) ESD robustness of a mixed-voltage I/O circuit can be increased /spl sim/60% by this substrate-triggered design.     

Bipolar SCR ESD devices

This paper presents a review of the recent studies based on the concept of Bipolar Silicon Controlled Rectifier (BSCR) devices across a variety of BiCMOS technologies. Examples of both BSCR design and application are presented, ranging from a 0.25 μm Si–Ge process with a shallow epi-layer, up to 250 V bipolar process. The BSCR device characteristics are discussed based on both 2-D physical process and device simulation and by the test structure ESD characterization.     

On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process

A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-/spl mu/m salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.     

SCR ESD protection with reduced trigger voltage

A novel silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection compatible with the advanced deep submicron triple well CMOS technologies is presented. By forward biasing the p-well/cathode junction, while keeping the n-well floating during ESD, the SCR trigger and holding voltages coincide at /spl sim/1 V. This value can be increased by a composite SCR/diode string circuit.     

Lateral SCR devices with low-voltage high-current triggeringcharacteristics for output ESD protection in submicron CMOS technology

A high-current PMOS-trigger lateral SCR (HIPTSCR) device and a high-current NMOS-trigger lateral SCR (HINTSCR) device with a lower trigger voltage but a higher trigger current are proposed to improve ESD robustness of CMOS output buffer in submicron CMOS technology. The lower trigger voltage is achieved by inserting short-channel thin-oxide PMOS or NMOS devices into the lateral SCR structures. The higher trigger current is achieved by inserting the bypass diodes into the structures of the HIPTSCR and HINTSCR devices. These HIPTSCR and HINTSCR devices have a lower trigger voltage to effectively protect the output transistors in the ESD-stress conditions, but they also have a higher trigger current to avoid the unexpected triggering due to the electrical noise on the output pad when the CMOS ICs are in the normal operating conditions. Experimental results have verified that the trigger current of the proposed HIPTSCR (HINTSCR) is increased up to 225.5 mA (218.5 mA). But, the trigger voltage of the HIPTSCR (HINTSCR) remains at a lower value of 13.4 V (11.6 V). The noise margin against the overshooting (undershooting) voltage pulse on the output pad, without accidentally triggering on the HINTSCR (HIPTSCR), can be greater than VDD+12 V (VSS -12 V). These HIPTSCR and HINTSCR devices have been practically used to protect CMOS output buffers with a 4000-V (700-V) HEM (MM) ESD robustness but only within a small layout area of 37.6×60 μm² in a standard 0.6-μm CMOS technology without extra process modification     

Novel and robust silicon-controlled rectifier (SCR) based devices for on-chip ESD protection

Silicon-controlled rectifiers (SCRs) are frequently used to build on-chip electrostatic discharge (ESD) protection structures, but SCRs are not sufficiently robust to meet a wide range of ESD requirements in various integrated circuits. In this paper, a novel and robust SCR-based device called the HHLVTSCR is presented. It is demonstrated that HHLVTSCR can exhibit various characteristics useful for ESD solutions. An example is also included to illustrate how HHVLTSCRs can be used to provide ESD protection to a practical application.     

Compact MOS-triggered SCR with faster turn-on speed for ESD protection

The merged and compact MOS-triggered SCR devices have been compared and investigated in a 0.13 μm CMOS process. From experimental results, the turn-on time of compact MOS-triggered SCR has been improved from ～7.2 ns of merged MOS-triggered SCR to ～4 ns. Compared to merged MOS-triggered SCR devices, the compact MOS-triggered SCR devices can achieve a lower trigger voltage, a faster turn-on speed, a lower on-resistance, a lower clamping voltage and a higher failure current.     

便携设备的ESD保护器件

随着移动电话、PDA、MP3播放机以及数码相机等的迅速发展,便携电子设备需求出现热潮,消费者正要求越来越先进的性能。将来的便携电子设备不仅要能够处理基于数据的正文,而且还要改善图形乃至视频率信息处理能力。与此同时,一方面要求设计者削减元件数量和减小电路板占用的空间,另一方面还要保证达到适当的EMI和ESD的抑制标准。特别是将来,采用亚微米工艺和甚精细线条宽度布线的复杂半导体功能电路,对电路瞬变过程的影响更加敏感,将导致上述的问题更加激化起来。 此外,在工业标准方面,欧共体的IEC 61000-4-2已     

ESD保护器件在多晶硅上的实现

静电放电现象是导致集成电路损坏的一个重要原因,目前绝大多数集成电路中的ESD保护电路都是在硅片上实现的,这将占用一定的硅片面积,提升电路的成本.如果能够在多晶硅层(垂直空间)实现ESD保护器件,就能够节约一定的面积,从而节约成本.介绍了对于在多晶硅上实现的静电保护器件的研究结果.     

ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology

This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the human-body-model (HBM) ESD level of this new proposed I/O cells can be greater than 5 kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of the I/O cell.     

Time-To-Latch-Up investigation of SCR devices as ESD protection structures on 65 nm technology platform

The purpose of this work was to study the influence of different layout parameters on the electrical performances and Time-To-Latch-Up (TTLU) by means of the injection of substrate current on SCR devices to be used as ESD protection structures for the 65 nm Flash memory technology platform. Low (1.2 V) and high (5.0 V) voltage class devices were studied in DC and 100 ns TLP regimes, and an ad hoc setup was developed to investigate TTLU as a function of the injected current needed to Latch-Up HV-SCRs. Results were then compared to 2D device simulations.     

Using an SCR as ESD protection without latch-up danger

A properly designed Low-Voltage Triggering SCR has a four times better ESD performance than a conventional grounded-gate NMOST of the same width. But it does present a latch-up risk due to its low holding voltage. The holding voltage can be increased by using a larger anode-to-cathode spacing, but at very large spacings the ESD performance decreases. It is shown that a window in SCR anode-to-cathode spacing exists, for which the holding voltage is sufficiently large, while the excellent ESD protection properties are preserved.     

Stacked zener trigger SCR for HV IC ESD protection

In HV BCD technology, SCR cannot been directly used as ESD protection owing to its high trigger voltage and low holding voltage. Stacked zener trigger SCRs for HV ESD protection is proposed and Compared to the traditional SCR. The proposed devices are fabricated with 0.35 um BCD process on P-type bulk wafers without buried layer. TLP testing results show that the single zener trigger SCR with 50 um width has a 6.7 V trigger voltage and 4.1 A failure current It2. Stacked 4 zener trigger SCRs is designed for 24 V I/O ESD protection, which has 8 V holding voltage, 27 V trigger voltage and pass7 KV HBM.     

SCR operation mode of diode strings for ESD protection

Diodes and diode strings in 90 nm and beyond technologies are investigated by measurement and device simulation. After a thorough calibration, the device simulator is utilised to achieve a better understanding and an enhanced device performance of diode strings under static and transient ESD conditions. Thereto, parasitic transistors and a so far neglected parasitic thyristor (SCR) in the diode string are regarded, exploited and optimised.     

New substrate-triggered ESD protection structures in a 0.18-μm CMOS process without extra mask

In order to quickly discharge the electrostatic discharge (ESD) energy, new substrate-triggered ESD protection structures are proposed in this work. Under transmission line pulsing (TLP) stress, the trigger voltage, turn-on speed and second breakdown current can be obviously improved, as compared with the traditional protection structures. From the experimental results, the new designs have proven a more effective ESD robustness. Moreover there is no need to add any extra mask or do any process modification for the new structures. The proposed new substrate-triggered structures have been verified in foundry’s 0.18-μm CMOS process.     

A novel SCR ESD protection for triple well CMOS technologies

A novel SCR structure for on-chip ESD protection implemented with a deep submicron triple well CMOS technology is presented. The triple well technology offers the possibility of biasing the p-well, on which the structure is built, under transient ESD stress conditions and independently from the substrate. This greatly affects the turn on mechanism of the structure. Unlike conventional SCR devices, the proposed p-well coupled SCR offers a reduced triggering voltage level as well as the enhanced ESD performance of the SCR devices. The turn on of this structure is realized with a common RC trigger network. The concept is supported by device simulation results     

多指条nMOSFET抗ESD设计技术

利用多指条nMOSFET进行抗ESD设计是提高当前CMOS集成电路抗ESD能力的一个重要手段，本文针对国内某集成电路生产线，利用TLP(Transmission Line Pulse)测试系统，测试分析了其nMOSFET单管在ESD作用下的失效机理，计算了单位面积下单管的抗ESD(Electro Static Discharge)能力，得到了为达到一定抗ESD能力而设计的多指条nMOSFET的面积参数，并给出了要达到4000V抗ESD能力时保护管的最小面积，最后通过ESDS试验进行了分析和验证。     

Design and optimization of LDMOS-SCR devices with improved ESD protection performance

The lateral diffusion metal-oxide semiconductor embedded silicon controlled rectifier (LDMOS-SCR) devices with optimized structures and layouts for improving the electrostatic discharge (ESD) protection ability have been proposed. The devices are designed and fabricated in 0.25-μm, 0.35-μm and 0.5-μm Bipolar-CMOS-DMOS processes. Firstly, by designing an appropriate stripe resistance in series with the source of the LDMOS-SCR, the holding voltage of the proposed high resistance LDMOS-SCR (HRLDMOS-SCR) increases. Secondly, by inserting a floating Zener-diode into the LDMOS-SCR, the trigger voltage of the modified Zener-diode triggered LDMOS-SCR (ZTLDMOS-SCR) decreases. Finally, the ZTLDMOS-SCR is further optimized by using a ring layout and incorporating a square source resistance, resulting in a significantly improved figure of merit in comparison to traditional LDMOS-SCR devices. The optimized ZTLDMOS-SCR devices are very attractive for constructing effective and latch-up immune high voltage ESD protection solutions in power integrated circuits.     

A new low-parasitic polysilicon SCR ESD protection structure for RF ICs

Robust low-parasitic electrostatic discharge (ESD) protection is highly desirable for RF ICs. This letter reports design of a new low-parasitic polysilicon silicon controlled rectifier (SCR) ESD protection structure designed and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology. The concept was verified by simulation and experiment with the results showing that the new structure has much lower parasitic capacitance (C/sub ESD/) and higher F-factor than that of other ESD protection devices. A small polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high human body model ESD protection of 3.2 kV while featuring a high F-factor of /spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR ESD protection structure seems to be an attractive solution to high-GHz RF ICs.     

A novel power-clamp assisted complementary MOSFET for robust ESD protection

A novel power-clamp assisted complementary MOSFET (PCACMOS), modified from traditional gate-coupled complementary MOSFET (GCCMOS), is proposed for high robust ESD (Electrostatic discharge) protection application. The power-clamp achieves by RC-NMOS and designs by Spice simulation. The comprehensive performance of the protection schemes are evaluated by the figure of merit (FOM). Compared with traditional gate-coupled MOSFET (GCCMOS) protection scheme, the power-clamp assisted complementary MOSFET (PCACMOS) protection scheme has a similar turn-on speed but higher FOM.