2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。     

2.5Gb/s 0.35μm CMOS光接收机前置放大器设计

采用0.35 μm CMOS工艺设计并实现了用于SDH系统STM-16(2.5 Gb/s)速率级光接收机前置放大器.此放大器采用+5 V电源电压,中频增益为73 dBΩ,3 dB带宽为2.2 GHz.核面积为0.15 mm×0.20 mm.     

10Gb/s0.18μm CMOS光接收机前置放大器

采用TSMC0．18μm CMOS工艺,设计应用于SDH系统STM-64速率级（10 Gbit／s）光接收机前置放大器,该前置放大器采用具有低输入阻抗、宽带宽特点的RGC形式的跨阻放大器实现,同时在电路中引入有源电感实现并联峰化技术,以拓展前置放大器的带宽。整个电路采用1．8V单电压源供电。仿真结果表明：中频互阻增益为59.2dBΩ,-3dB带宽为9．08GHz．     

12×10Gb/s CMOS并行光接收机前置放大器阵列设计

采用SMIC 0.18 μm CMOS工艺,设计了一种12路并行、每路工作速率为10Gb/s的光接收机前置放大器阵列,应用于高速芯片间的光互连.整个电路通过1.8V电压供电,采用RGC结构和有源电感并联峰化技术,单路中频跨阻增益为47.1dBΩ,-3dB带宽为8.9GHz.芯片工作时总的传输速率为120Gb/s.     

10Gb/s 0.18μm CMOS光接收机前端放大电路

介绍了利用TSMC 0.18μm CMON工艺设计的应用于SDH STM-64速率级(10Gb/s)光接收机前端放大电路。该电路由前置放大器和作为主放大器的限幅放大器构成,其中前置放大器采用RGC形式的互阻放大器实现,限幅放大器采用改进的Cherry—Hooper结构。模拟结果表明该电路可以工作在10Gb/s速率上。     

10Gb/s光接收机跨阻前置放大器芯片设计研究

采用0.18 μm BiCMOS工艺设计并实现了一种高增益、低噪声、宽带宽以及大输入动态范围的光接收机跨阻前置放大器.在寄生电容为250 fF的情况下,采用全集成的四级放大电路,合理实现了上述各项参数指标间的折中.测试结果表明:放大器单端跨阻增益为73 dB,-3 dB带宽为7.6 GHz,灵敏度低至-20.44 dBm,功耗为74 mW,最大差分输出电压为200 mV,最大输入饱和光电流峰-峰值为1 mA,等效输入噪声为17.1 pA/√Hz,芯片面积为800 μ.m×950μm.     

光通信用宽动态范围10 Gb/s CMOS跨阻前置放大器

采用UMC 0.13 μm CMOS工艺,设计了一种应用于SDH系统STM-64(10 Gb/s)光接收机前置放大器.该前置放大器采用具有低输入阻抗特点的RGC形式的跨阻放大器实现.同时,引入消直流电路来扩大输入信号的动态范围.后仿真结果表明:双端输出时中频跨阻增益约为57.6 dBΩ,-3 dB带宽为10.7 GHz,平均等效输入噪声电流谱密度为18.76 pA/sqrt(Hz),1.2V单电压源下功耗为21 mW,输入信号动态范围40 dB(10 μA～1 mA).芯片面积为0.462 mm×0.566 mm.     

2.5Gb/s宽动态范围光接收机前端放大电路设计

基于UMC 0.18μm CMOS工艺,设计了一种2Gb/s传输速率的宽动态范围光接收机前端放大电路。采用对数放大器来增大接收机的输入动态范围,前置放大器采用差分共源跨阻放大器,并使用有源电感做负载来增大带宽。实验结果表明:该接收机前端电路的增益为80dB,3dB带宽为2.3GHz,2.5Gb/s输出眼图良好,输入动态范围为60dB(1μA～1mA)。     

0.18μm CMOS 10Gb/s光接收机限幅放大器

利用TSMC 0.18μm CMOS工艺设计了应用于SDH系统STM-64(10 Gb/s)速率级光接收机中的限幅放大器.该放大器采用了改进的Cherry-Hooper结构以获得高的增益带宽积,从而保证限幅放大器在10Gb/s以及更高的速率上工作.测试结果表明,此限幅放大器在10Gb/s速率上,输入动态范围为42dB(3.2mV~500mV),50Ω负载上的输出限幅在250mV,小信号输入时的最高工作速率为12Gb/s.限幅放大器采用1.8 V电源供电,功耗110mW.芯片的面积为0.7mm×0.9mm.     

光通信系统中前置跨阻放大器的研究和设计

本文介绍了前置跨阻放大器在光通信中光接收机上的应用及其发展方向，提出了一种新型的前置跨阻放大器电路结构，即在普通跨阻结构上适当地加了有源反馈的电路结构，并对它们进行了理论分析，最后用BSIM3v3模型，0．35μm工艺，Cadence仿真器工具对它们进行仿真，结果很好，带宽从lGHz增加到2．15GHz。     

A RGC-based,low-power,CMOS transimpedance amplifier for 10Gb/s optical receivers

ABSTRACT

In this paper, a new low-power transimpedance amplifier (TIA) based on a modified Regulated Cascode (RGC) circuit structure followed by a closed-loop post-amplifier is proposed for 10 Gb/s applications. The main objective of this work is to reduce the power consumption while, the frequency bandwidth of the proposed amplifier is increased considerably. The booster of a conventional RGC is modified by a cascoded transistor and its effect on the performance of the circuit is studied mathematically, which are verified by simulations. The bandwidth extension is occurred due to increasing the gain of the booster amplifier in the RGC stage, which isolates further the input capacitance and results in a reduced input resistance value hence, a higher input pole frequency is obtained in comparison with other conventional RGC structures. On the other hand, by using an active inductive peaking technique, the frequency of the output pole is also increased which results in a further extension of the frequency bandwidth for the proposed circuit. The proposed TIA is simulated using 90 nm CMOS technology parameters, which shows a 50.5 dBΩ transimpedance gain, 7.3 GHz frequency bandwidth and 1.22 µA_rms input referred noise value for only 1 mW of power consumption at 1.2 V supply voltage.     

A 40 Gbit/s fully integrated optical receiver analog front-end in 90 nm CMOS

A fully integrated 40 Gbit/s optical receiver analog front-end (AFE) including a transimpedance amplifier (TIA) and a limiting amplifier (LA) for short distance communication is described in this paper.The proposed TIA employs a modified regulated cascode (RGC) configuration as input stage,and adopts a third order interleaving active feedback gain stage.The LA utilizes nested active feedback,negative capacitance,and inductor peaking technology to achieve high voltage gain and wide bandwidth.The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV(p p).Simulation results show that the receiver AFE provides conversion gain of up to 83 and bandwidth of 34.7 GHz,and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA(rms).     

1Gb/s CMOS调节型共源共栅光接收机

基于特许0.35μm EEPROM CMOS标准工艺设计了一种单片集成光接收机芯片,集成了双光电探测器(DPD)、调节型共源共栅(RGC)跨阻前置放大器(TIA)、三级限幅放大器(LA,limiting amplifier)和输出电路,其中RGCTIA能够隔离光电二极管的电容影响,并可以有效地扩展光接收机的带宽。测试结果表明,光接收机的3dB带宽为821MHz,在误码率为10-9、灵敏度为-11dBm的条件下,光接收机的数据传输速率达到了1Gb/s;在3.3V电压下工作,芯片的功耗为54mW。     

2.5Gb/s和3.125Gb/s速率级0.35μmCMOS限幅放大器

采用了TSMC0.35μm CMOS工艺实现了可用于SONET/SDH2.5Gb/s和3.125Gb/s速率级光纤通信系统的限幅放大器。通过在芯片测试其最小输入动态范围可达8mVp—p，单端输出摆幅为400mVp-p，功耗250mW，含信号丢失检测功能，可以满足商用化光纤通信系统的使用标准。     

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ transimpedance gain, 20.4-GHz −3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10⁻¹² BER at 26 Gb/s for a 2¹⁵−1 PRBS input with a −7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.     

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10~(-9). The chip dissipates 60 mW under a single 3.3 V supply.     

基于标准CMOS工艺的1.5Gb/s单片集成光接收机

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10-9. The chip dissipates 60 mW under a single 3.3 V supply.