低功耗SARADC芯片设计与研究

本文设计和研究了一种低功耗8Bit SARADC结构,其采用了GF0.18um工艺设计,1.8V单电源电压,动态范围为1V, INL为0.5LSB,DNL为2LSB通过详细的电路原理分析和软件Cadence的仿真,并流片测试,性能达到设计初衷。     

二维DCT图像处理器的低功耗实现

本文提出了一种基于矩阵向量乘法器的低功耗二维DCT结构,该结构通过最大限度地共享矩阵向量乘法中的乘积因子降低二维DCT中的乘法计算量,实现低功耗计算.此外,该二维DCT设计支持对矩阵向量乘法器的计算精度控制,从而实现对二维DCT处理器的低功耗调整.FPGA硬件平台的实际验证结果表明,与传统的基于移位累加乘法器的二维DCT设计相比,本设计可以节省35%以上的功耗.     

汽车BCM的低功耗设计及实现

本文针对集成了远程无钥匙进入(RKE)功能的车身控制模块(BCM)设计了一种低功耗方案,为部分电路设计了可程控供电电源,以实现在满足休眠条件时,通过禁能部分电路的供电降低电流消耗,同时设置内部唤醒定时器,使得BCM在低功耗模式中可以被临时唤醒,以判断遥控钥匙的操作,同时针对空间干扰引起的射频毛刺设计了过滤机制,能够自动屏蔽外部RF干扰引起的假唤醒,进一步降低了低功耗模式下BCM的整体功耗.     

低功耗非制冷红外图像处理专用SoC芯片

非制冷红外成像技术具有非常广泛的应用前景。但是,目前非制冷红外成像芯片存在非均匀校正、图像细节增强和条纹噪声等亟待解决的问题。论文提出并设计一种面向非制冷红外成像的图像处理专用SoC芯片,芯片集成了一个CPU、两个DSP处理器和一个红外图像处理专用加速器,单芯片可实现非制冷低功耗红外图像的非均匀校正、图像滤波、直方图均衡、数字图像细节增强、条纹消除和目标检测跟踪等实时图像处理。同时,研究开发了面向芯片应用的非制冷低功耗红外图像处理算法。采用65-nm CMOS工艺实现了非制冷红外图像专用处理SoC芯片,实现了基于非制冷红外成像芯片和图像处理SoC芯片的小型低功耗非制冷红外成像系统。测试结果表明成像系统可以实现清晰的非制冷红外成像、目标检测及目标跟踪等功能,系统功耗小于2 W,体积相比传统的系统减小了50%,满足对体积、功耗、性能要求比较高的系统的应用需求,具有较高的工程应用价值和前景。     

电源管理芯片过温保护电路的分析与设计

保护电路是电源管理芯片的一个重要环节,研究一种高可靠的保护电路是非常重要的。为了保证电源管理芯片在复杂的环境中可以正常使用,本文主要对其中的保护电路进行了详细的分析,并设计出过温保护电路。根据可重用性的设计方法,在CSMCO．5μm工艺下,利用Cadence spectreI具对过温保护电路进行前端仿真验证。在不同电源电压下,对保护功能开启时的温度、滞迟范围、滞迟开启温度都进行了仿真测试。通过滞迟模块既有效抑制了芯片温度的升高,又避免频繁对功率管的关断。     

集成电路低功耗设计方法

信息化的社会发展无法离开电子产品的不断进步,而其对其低功耗的设计要求正在不断增强.但当前电子产品的功能质量在提高的同时,其功耗设计却没能跟上设计的要求,一直处于上升趋势,这将对电子产品性能的提高产生一定的影响.一款经久耐用、性能强的电子产品必须具备水平相当的低功耗设计方式.本文主要探讨了集成电路的低功耗设计方法,以作为相关参考.     

集成电路低功耗设计方法

针对当前集成电路低功耗的需求,对当前几种常用的低功耗设计方法和技术进行探讨,包括算法优化、工艺优化、版图优化、门级优化等,从而为当前继承电路优化提供借鉴参考。     

Low power dual-port CMOS SRAM macro design

A novel low power dual-port CMOS SRAM structure is described. The inherent low power advantage is obtained by using current-mode rather than voltage-mode signal transmission. The design of this new dual-port memory cell and current-mode sense amplifier is based on 0.5 μm, 5 V CMOS logic process technology. HSPICE simulations show that the circuits can operate at high speed even if the supply voltage is reduced to 2 V. The dual-port memory cell is most suitable for the design of FIFO buffers     

Low power design of multi-modulus programmable frequency divider

A novel low power multi-modulus programmable divider is presented. It employs the division ratio control-bits (DRCBs) to cut off the current of certain latches on occasion, which then have no contribution to the operation of the entire divider. The proposed structure allows a power reduction up to 50%.     

Low power design using double edge triggered flip-flops

In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flip-flops and single edge triggered flip-flops is compared via architectural level studies, analytical considerations and simulations. The analysis includes an implementation independent study on the effect of input sequences in the energy dissipation of single and double edge triggered flip-flops. The system level energy savings possible by using registers consisting of double edge triggered flip-flops, instead of single edge triggered flip-flops, is subsequently explored. The results are extremely encouraging, indicating that double edge triggered flip-flops are capable of significant energy savings, for only a small overhead in complexity     

Low power design of variable centre frequency CMOS VCO

This paper reports design of a voltage controlled oscillator (VCO) for low power consumption and generation of variable centre frequencies. The current starved technique is used for design of VCO. In normal current starved VCO circuits the centre frequency remains fixed, but here the circuit is designed for generating different centre frequencies, which makes the VCO more versatile. It can generate more frequencies with better resolution. The centre frequency and power dissipation both depend on the number of stages which is selectable. Power dissipation of VCO is estimated based on mathematical modelling and compared with simulation results. Extensive simulations along with performance evaluation of VCO is done to check output frequency and power dissipation. Best simulation results obtained on Tanner EDA tool show that centre frequency can be varied from 3.04 to 9.76 MHz through stage selection. Also, a reduction in power dissipation is obtained from 330 mW to 210 mW through stage selection.     

密码芯片中抗差分功耗分析攻击的DES方案设计

功耗分析攻击是当前密码芯片中各类数据加密算法的主要安全威胁,尤其是对于迄今应用最为广泛的数据加密标准算法造成了严重的危害。通过分析数据加密标准算法遭受功耗分析攻击的原理,并结合针对数据加密标准算法关键防御技术,给出了一种基于互补电路的中间值掩码DES方案设计。主要是利用双电路进行互补输出,以保证寄存器翻转保持功耗恒定,从而最大限度地降低功耗差异。根据算法性能分析结果表明：该方案可以抵抗差分功耗分析攻击,且实现简单,能够直接应用于密码芯片的电路设计中。     

Computer-aided design of a BPSK spread-spectrum chip set

The design of a binary-phase shift-keyed (BPSK) spread-spectrum chip set with an integrated CAD environment called VANDA is described. VANDA uses the functional compiler concept to integrate system and physical designs, thus allowing complex high-performance integrated circuit chips to be implemented easily. Three functional compilers have been designed and implemented for the design of a spread-spectrum transceiver: a pseudonoise (PN) generator compiler, a direct digital frequency synthesizer (DDFS) compiler, and a Costas loop compiler. Three test chips for a BPSK digital intermediate frequency (IF) spread-spectrum system generated by these compilers have been fabricated and tested. Details of each of the functional compilers and the test chips are described. In addition, the measurement results for digital IF transceiver test boards constructed using these chips are presented     

电网现场标准化作业管理系统的信息化设计

为了改变目前电网现场作业管理的变电巡检、变电检修试验、输电线路巡捡检修等管理系统各自独立运行,信息不能共享,功能、效率受限,建设和维护成本高的现状,提出了采用B/S+C/S构架模式,将各现场作业管理模块和生产MIS(管理系统)集成为一体的现场作业管理系统的设计方案,做到各子系统和生产MIS软硬资源共享,做到同一数据唯一入口、一处录入多处使用.各子系统设备人员等基础信息来源于生产管理系统,各子系统又是生产管理系统的作业数据、缺陷信息的重要来源.经过研究试用成功和推广应用,目前该系统已在江西电网220 kV及以上变电站全面应用.     

Low power design for DSP: methodologies and techniques

Power dissipation is becoming a limiting factor in the realization of VLSI systems. The principal reasons for this are maximum operating temperature and, for portable applications, battery life. Because of the relatively greater complexity, the power dissipation in digital signal processing (DSP) applications is of special significance, and low power design techniques are now emerging. This paper provides an overview of the techniques and methodologies that have emerged in the past few years for DSP system design. These include techniques for minimizing power at architectural and algorithmic levels including DSP programming issues. In addition, the paper indicates some potential design directions.     

From chip to inverter: Electro-thermal modeling and design for paralleled power devices in high power application

Power loss and thermal stress of semiconductor components are closely related to the reliability of high power inverter. In addition to the inverter electrical parameters, the size of semiconductor is also an important factor in inverter electro-thermal performance. In this paper, an electro-thermal model correlated with chip area and chip paralleled number is built to calculate the power switch loss and junction temperature. Then, the relationship between chips size and inverter loss/thermal behaviors can be established by this model, enabling more flexible in chip design to optimize the inverter efficiency and thermal loading. Finally, the inverter electro-thermal design procedure is established to properly select the chip area and number in a power switch. As a case study, the optimal chip paralleled structure in the high power inverter is estimated and the results are compared under varying inverter output frequency. By selecting the chip area and number in the target region, junction temperature can maintain in the limited range.     

多模终端待机低功耗设计

如今的移动通信网络是由多种制式及多个频段融合而成的多模网络,对于商用终端而言,多种难题交织在一起,其中待机时长是必须要解决的一个关键问题.为此,不同于传统增大电池容量的方法,采用降低待机功耗的策略:时域的时隙控制、频域的电流控制、睡眠和唤醒的电源门控制、低频时钟高频化,其中高频时钟校准低频时钟是降低睡眠态功耗的关键措施.这一系列方案的实施,使得终端在多模实际网络环境下的待机电流小于5 mA,终端的待机低功耗达到了有竞争力的商用水平.     

Color reproduction of a single chip color camera with a frame transfer CCD

A single chip color camera of phase separation type employing a 512 V/spl times/486 H element frame transfer CCD with a high color fidelity has been fabricated. The horizontal color crosstalk is successfully suppressed by using a color stripe filter array in which optically opaque stripes are vertically aligned on the channel stop regions of the CCD.