共查询到18条相似文献,搜索用时 156 毫秒
1.
对于VLSI中具有邻域子空间的电路模块,提出了一种高效测试生成方法.利用该方法得到了行波进位、超前进位加法器的测试生成,并予以了硬件实现.8位、16位和32位两种加法器的测试实验表明,这些测试生成能够使单固定型故障的故障覆盖率达到100%,双故障覆盖率分别达到99.996%以上以及100%,故障定位率得到了显著提高.测试矢量的数目仅与邻域子空间的大小有关.由于原电路中加法器的复用,两种加法器测试生成的硬件实现仅需额外的一个逻辑与门,将硬件开销降至最小. 相似文献
2.
3.
电路测试神经网络方法中求多个测试矢量 总被引:7,自引:0,他引:7
文章研究在数字电路测试的神经网络方法中求给定故障对应的多个测试矢量的方法,首先提出了一种求多个测试矢量的遗传进化方法,然后提出了一种矢量扰动方法,通过这两种者的结合使用,能获得被测电路较小的完备测订,从而提高了电路测试神经网络的方法的性能。 相似文献
4.
5.
基于模块化结构的N位加法器的测试生成 总被引:2,自引:0,他引:2
针对单个stuck-at故障,研究了N位加法器的测试矢量生成问题,对于行波进位加法器,只需8个测试矢量就可得到100%的故障覆盖率;对于N位先行进位加法器,只需N^2+2N+3个测试矢量即可得到100%的故障覆盖率。 相似文献
6.
7.
8.
神经网络在组合电路故障模拟测试生成算法中的应用 总被引:8,自引:0,他引:8
本文在基于故障模拟的测试生成算法基础上,提出了一种初始测试矢量的生成方法,即采用神经元网络模型来生成初始矢量,既避免了随机生成初始矢量的盲目性,又避免了确定性算法使用回溯所带来的大运算量。试验结果证明这种方法是有效的。 相似文献
9.
10.
11.
A. N. Nagamani S. Ashwin B. Abhishek V. K. Agrawal 《Journal of Electronic Testing》2016,32(2):175-196
Reversible logic has gained interest of researchers worldwide for its ultra-low power and high speed computing abilities in the future quantum information processing. Testing of these circuits is important for ensuring high reliability of their operation. In this work, we propose an ATPG algorithm for reversible circuits using an exact approach to generate CTS (Complete Test Set) which can detect single stuck-at faults, multiple stuck-at faults, repeated gate fault, partial and complete missing gate faults which are very useful logical fault models for reversible logic to model any physical defect. Proposed algorithm can be used to test a reversible circuit designed with k-CNOT, Peres and Fredkin gates. Through extensive experiments, we have validated our proposed algorithm for several benchmark circuits and other circuits with family of reversible gates. This algorithm produces a minimal and complete test set while reducing test generation time as compared to existing state-of-the-art algorithms. A testing tool is developed satisfying the purpose of generating all possible CTS’s indicating the simulation time, number of levels and gates in the circuit. This paper also contributes to the detection and removal of redundant faults for optimal test set generation. 相似文献
12.
组合电路桥接故障诊断的测试生成及优化 总被引:1,自引:0,他引:1
在利用划分等价类的方法来诊断组合电路中桥接故障的基础上,本文提出了一种基于门特性的IDDQ测试集生成算法及对测试集排序筛选的优化方法.实验结果表明,将此方法应用于组合电路桥接故障的诊断可缩减测试集的大小,提高诊断的故障覆盖率. 相似文献
13.
Ting Long Houjun Wang Shulin Tian Jianguo Huang Bing Long 《Journal of Electronic Testing》2010,26(4):419-428
This paper proposes a test generation algorithm combining genetic algorithm for fault diagnosis on linear systems. Most test
generation algorithms just used a single value fault model. This test generation algorithm is based on a continuous fault
model. This algorithm can improve the treatment of the tolerance problem, including the tolerances of both normal and fault
parameters, and enhance the fault coverage rate. The genetic algorithm can be used to choose the characteristic values. The
genetic algorithm can enhance precision of test generation algorithm especially for complex fitness functions derived from
complex systems under test. The genetic algorithm can also further improve the fault coverage rate by reducing the loop number
of divisions of the initial fault range. The experiments are carried out to show this test generation algorithm with a linear
system and an integrated circuit. 相似文献
14.
Gupta P. Jha N. K. Lingappan L. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(1):24-36
In this paper, we present a test generation framework for quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted recent significant attention and shows promise as a viable future technology. This work is motivated by the fact that the stuck-at fault test set of a circuit is not guaranteed to detect all defects that can occur in its QCA implementation. We show how to generate additional test vectors to supplement the stuck-at fault test set to guarantee that all simulated defects in the QCA gates get detected. Since nanotechnologies will be dominated by interconnects, we also target bridging faults on QCA interconnects. The efficacy of our framework is established through its application to QCA implementations of MCNC and ISCAS'85 benchmarks that use majority gates as primitives 相似文献
15.
The scan design is the most widely used technique used to ensure the testability of sequential circuits. In this article it is shown that testability is still guaranteed, even if only a small part of the flipflops is integrated into a scan path. An algorithm is presented for selecting a minimal number of flipflops, which must be directly accessible. The direct accessibility ensures that, for each fault, the necessary test sequence is bounded linearly in the circuit size. Since the underlying problem is NP-complete, efficient heuristics are implemented to compute suboptimal solutions. Moreover, a new algorithm is presented to map a sequential circuit into a minimal combinational one, such that test pattern generation for both circuit representations is equivalent and the fast combinational ATPG methods can be applied. For all benchmark circuits investigated, this approach results in a significant reduction of the hardware overhead, and additionally a complete fault coverage is still obtained. Amazingly the overall test application time decreases in comparison with a complete scan path, since the width of the shifted patterns is shorter, and the number of patterns increase only to a small extent. 相似文献
16.
Sandip Kundu Sujit T. Zachariah Sanjay Sengupta Rajesh Galivanche 《Journal of Electronic Testing》2001,17(3-4):209-218
Device scaling has led to the blurring of the boundary between design and test: marginalities introduced by design tool approximations can cause failures when aggressive designs are subjected to process variation. Larger die sizes are more vulnerable to intra-die variations, invalidating analyses based on a number of given process corners. These trends are eroding the predictability of test quality based on stuck-at fault coverage. Industry studies have shown that an at-speed functional test with poor stuck-at fault coverage can be a better DPM screen than a set of scan tests with very high stuck-at fault coverage. Contrary to conventional wisdom, we have observed that a high stuck-at fault test set is not necessarily good at detecting faults that model actual failure mechanisms. One approach to address the test quality crisis is to rethink the fault model that is at the core of these tests. Targeting realistic fault models is a challenge that spans the design, test and manufacturing domains: the extraction of realistic faults has to analyze the design at the physical and circuit levels of abstraction while taking into account the failure modes observed during manufacture. Practical fault models need to be defined that adequately model failing behavior while remaining amenable to automatic test generation. The addition of these fault models place increasing performance and capacity demands on already stressed test generation and fault simulation tools. A new generation of analysis and test generation tools is needed to address the challenge of defect-based test. We provide a detailed discussion of process technology trends that are responsible for next generation test problems, and present a test automation infrastructure being developed at Intel to meet the challenge. 相似文献
17.
文章提出的模糊化的时序电路测试生成算法不明确指定故障点的故障值,它将故障值模糊化,并以符号表示。本算法第一阶段通过计算状态线和原始输出端的故障值来寻找测试矢量,通过计算故障点的正常值来 寻找测试矢量对应的故障类型;第二阶段用故障点的正常值作为约束条件计算故障点的另一个测试矢量。与传统的算法不同,它不需要回退和传播的过程。实验结果表明本算法具有较高的故障覆盖率和较少的测试时间。 相似文献
18.
Gupta P. Zhang R. Jha N.K. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(8):1035-1045
We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs), single electron transistor (SET), and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this type of logic. We have built the first automatic test pattern generator and fault simulator for threshold logic which has been integrated on top of an existing computer-aided design (CAD) tool. These exploit new fault collapsing techniques we have developed for threshold networks. We perform fault modeling, backed by HSPICE simulations, to show that many cuts and shorts in RTD-based threshold gates are equivalent to stuck-at faults at the inputs and output of the gate. Experimental results with the MCNC benchmarks indicate that test vectors were found for all testable stuck-at faults in their threshold network implementations. 相似文献