基于偏置继电反馈的闭环辨识方法

多变量过程对象通常具有耦合性等特点,而在对其解耦过程中一般存在一些回路含有不可操作的变量,这就给对象的辨识带来了难度。文中提出了一种基于偏置继电反馈的闭环辨识方法,通过对回路进行偏置继电反馈实验实现对象辨识。文中方法将实验获取对象的输入输出信号进行分析和研究,获取对象在重要频率范围内的频率特性,从而辨识出对象模型。仿真实验表明,文中方法适用于广泛的过程对象,且具有较好的准确性和鲁棒性。     

水箱模型辨识及PID参数自整定技术研究

为了达到对液位控制模型进行实时模型参数辨识,并实时计算出较为理想的PID参数对水箱进行实时控制的目的,采用最小二乘算法改进法及基于Ziegler-Nichols整定法的改良公式,进行水箱液位控制实验。得到对水箱液位进行实时控制的结果,其中超调量、控制时让均较为理想。结果证明此方法合理可行,具有对变化模型进行实时辨识的特点,结合动态辨识与基于模型的PID自整定法对非常规模型进行控制。     

基于MSC1210的多通道模糊PID控制器的设计

针对传统PID控制器对复杂控制对象的参数变化缺乏自适应性及多数PID仪表仅有单路控制输出的不足,设计了一种基于MSC1210的多通道模糊控制器,并对其原理及其设计方法做了简单介绍。该控制器可以同时控制多个被控对象,与LCD的结合实现了PID控制曲线的显示。     

基于自偏置技术的低噪声锁相环研究

文中描述了一种自偏置型锁相环电路,通过采用环路自适应的方法得到一个固定的阻尼系数ξ以及带宽和输入频率的比值ωN/ωREF,从而保证环路的稳定。传统锁相环电路设计需要一个固定的电荷泵充放电电流和固定的VCO增益,这样才能保持系统的稳定性。但是当工艺发展到深亚微米尤其是65 nm以下的时候,芯片的供电电压都在1 V以下且器件的二级效应趋于严重,此时要得到一个固定的电流值或者固定的VCO增益是很困难的。自偏置锁相环解决了这个问题,由于采用了自适应环路的设计方法,使得系统受工艺、温度和电压的影响非常小,而且锁定范围更大。可以广泛应用于时钟发生器以及通信系统。芯片采用SMIC标准低漏电55 nm CMOS工艺制造,测试均方抖动为3.8 ps,峰-峰值抖动25 ps。     

继电反馈辨识算法研究及其软件实现

主要针对继电反馈的传统方法和带有不对称滞环方法进行分析比较,通过理论分析和MATLAB仿真,得出两种算法的优缺点。进而将这两种算法应用于PIDTune辨识软件,然后通过对罗克韦尔仿真软件的仿真实验和对实际数据的辨识结果,得出两种算法在实际应用中能更有效地进行系统辨识。     

软件锁相环及锁相环替代技术

锁相环的锁相能力是影响锁相环性能的重要因素。本文介绍了当前主流软件锁相环系统的原理、结构,以及锁相环改进与替代方法,对各种软件锁相环方法的锁相效果、抗扰性能、运算速度、适应场合等进行了详细分析与介绍,并通过MATLAB仿真进行了实验验证。     

基于数字锁相环的新型频相检测方法研究

在经典DPLL(数字锁相环)的基础上,提出了一种在中频过采样背景条件下利用过采样值进行相位捕捉和跟踪的新型数字锁相环。该方法利用两级鉴频器实现频率锁定,同时利用高频过采样实现数字锁相,对相位误差一步调整到位而不需连续多次调整。最后讨论了波形失真和随机抖动的影响;利用相对阈值法使性能得到很大改善。该方法解决了锁定精度和锁定时间不能同时兼顾以及抗干扰能力差等若干问题。     

平稳过程突变的在线检测与辨识

将稳健－容错辨识与突变检测技术相结合,在合理给出模型参数容错辨识算法的基础上,构造了一组实用、可靠的平稳过程脉冲型故障在线检测与幅度辨识算法;通过过程输出信息差分处理,合理地建立了阶跃型与脉冲型突变之间的转换关系,架起了利用脉冲型的故障检测与辨识方法处理阶跃型突变问题的桥梁;通过仿真计算,证实了检测与辨识算法的有效性。     

基于卡尔曼滤波的锁相环算法研究

在某卫星载荷—感应式磁力仪的设计中,需要提取高动态环境下的磁场信号并降低所获信号的噪声干扰。基于此提出了一种改进的基于卡尔曼滤波的锁相环设计算法并应用于感应式磁力仪数据处理单元DSP的软件设计中,设计采用扩展卡尔曼滤波方法结合传统全数字软件锁相环的方法对待测信号进行滤噪、跟踪,获取信号的频率信息并通过锁相放大器获取信号的幅值、相位信息,并进行了仿真和实验验证。实验结果表明,改进的锁相环可以有效的对多普勒频率变化率为f=500Hz/s,信噪比低至-20dB的信号进行跟踪。该方法已应用于感应式磁力仪地面设备的信号检测和提取。     

继电自整定PID控制算法比较研究

本文将粒子群优化算法与经典的PID继电自整定法相结合,利用粒子群优化算法对继电自整定获得的PID参数进行优化,并对结合了粒子群优化算法的继电自整定PID控制法与经典的继电自整定PID控制法进行了仿真,并对仿真结果进行了对比.     

基于MATLAB的锁相环频率合成器教学实践

通信系统性能好坏很大程度上取决于有没有一个良好的同步系统。在“通信原理”课程中提到了基于锁相环的同步系统,但是对这部分内容介绍简单,没有系统的推导以及结论。基于Matlab的锁相环系统,能够得到不同参数下的锁相环的环路滤波器幅频响应和闭环响应,在Simulink工具箱中,设计一个基于锁相环的频率合成器,让学生掌握锁相环相位锁定的原理以及同步系统,为通信原理课程学习提供了支持。     

一种基于环形振荡器的双环路锁相环

A dual-loop phase-locked loop（PLL）for wideband operation is proposed.The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one,enabling a wide tuning range and low voltage-controlled oscillator（VCO）gain without poisoning phase noise and reference spur suppression performance.An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized.A novel multiple-pass ring VCO is designed for the dual-loop application.It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology.The measured tuning range is from 4.2 to 5.9 GHz.It achieves a low phase noise of–99 dBc/Hz@1 MHz offset from a 5.5 GHz carrier.     

A multiple-pass ring oscillator based dual-loop phase-locked loop

A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled oscillator (VCO) gain without poisoning phase noise and reference spur suppression performance. An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application. It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology. The measured tuning range is from 4.2 to 5.9 GHz. It achieves a low phase noise of-99 dBc/Hz @ 1 MHz offset from a 5.5 GHz carrier.     

一种用于低电压集成锁相环的省面积的双通道环路滤波器

This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that of the integration-path CP.By adding voltages across these two paths,the zero-capacitance is magnified B times equivalently.As a result,the chip size is greatly reduced.Based on this LPF,a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18μm RFCMOS technology.Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that,at a frequency of 3.20 GHz,phase noise is–120.2 dBc/Hz at 1 MHz offset,reference spur is–72 dBc,and power is 24 mW.     

An area-saving dual-path loop filter for low-voltage integrated phase-locked loops

This paper proposes an area-saving dual-path loop filter (LPF) for low-voltage integrated phase-locked loops (PLLs). With this LPF, output current of the lowpass-path charge-pump (CP) is B times (B>1) as great as that of the integration-path CP. By adding voltages across these two paths, the zero-capacitance is magnified B times equivalently. As a result, the chip size is greatly reduced. Based on this LPF, a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18 μm RFCMOS technology. Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that, at a frequency of 3.20 GHz, phase noise is -120.2 dBc/Hz at 1 MHz offset, reference spur is -72 dBc, and power is 24 mW.     

基于FPGA的全数字锁相环设计与实现

针对模拟锁相环抗干扰能力差、可靠性不高,生产成本过高的弱点,采用Verilog编程语言,通过Quartus ii软件仿真,设计了一款基于FPGA的全数字锁相环。该锁相环能对输入数字信号进行快速地位同步时钟提取,并已经应用于以Altera公司生产的Cyclone iii系列FPGA芯片[1]为核心的软件无线电硬件平台的时钟同步提取当中。     

基于斜坡电荷泵控制的高速低抖动锁相环

本文提出了一种新型高速低抖动锁相环架构。通过实时监测鉴频鉴相器的输出产生线性斜坡电荷泵电流,实现了自适应带宽控制。主要通过在传统锁相环的基础上,巧妙地设计了一个快速启动电路和一个斜坡电荷泵电路。首先,使能快速启动电路实现对环路滤波器的快速预充电;然后当鉴频鉴相器输出的充电电流脉宽超过设定的最小值时,斜坡电流控制电路将线性增加电荷泵电流,从而实现了快速响应和低相位噪声。同时,通过零温度系数电荷泵电流的设计,保证了高速低抖动指标的温度稳定性。所设计的新型锁相环架构已在一款基于0.35 μm的DSP处理芯片中得到验证。测试结果显示所设计斜坡电荷泵锁相环在宽温度范围内使得锁定时间提高了60%,且峰峰值抖动仅有0.3%的良好特性。     

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop(PLL) characterized by a short locking time and low jitter is presented,which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector(PFD) to implement adaptive bandwidth control.This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL.First,the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter...     

A monolithic K-band phase-locked loop for microwave radar application

A monolithic K-band phase-locked loop(PLL) for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator(VCO) achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic(CML) divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency. Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components. The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of -0.84 dBm and phase noise of 91:92 dBc/Hz@1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm² without pads under a 1.2 V single voltage supply.     

锁相环在微机保护中的应用

针对微机保护中采用传统的采样方法,采样频率难以自动跟踪被测量的频率变化而发生变化,必然会导致FFT运算产生误差。本文采用锁相环同步采样技术实现对微机保护装置中交流电压、电流信号的频率和相位进行锁定,以提高测量精度和实时性。结合锁相环控制AD7656模数转换芯片的实验,证明整周期同步采样在微机保护装置中的可行性,解决了软件同步采样的实时性差、软件编写复杂等问题。