刻蚀设备在太阳能晶硅电池刻蚀工艺中的应用

介绍了激光划线设备在太阳能电池中的应用。与传统等离子体刻蚀设备对比,从设备结构,工艺原理,试验测试等方面做了深入的分析,并从理论角度分析得出激光刻蚀具备效率损失小,能够提高电池片的转换效率的优点,同时用实验验证了激光划片设备具有优异的刻蚀效果,对提升电池片效率的贡献。     

自动称重系统在全自动硅片上下料机的应用

以自主研发的刻蚀工序自动化设备为基础,设计上下料机自动称重系统,测量刻蚀工艺前后电池片的减薄量变化,为工艺优化提供有力数据支持,同时提高效率,避免人工称重对电池片的污染和产能的影响.     

背面刻蚀对单晶硅太阳电池性能影响的研究

为了减少太阳电池载流子的背面复合,采用离子束对沉积完SiNx减反射膜后的单面扩散和双面扩散的单晶硅片背面进行刻蚀,研究了刻蚀时间对太阳电池性能的影响.采用标准的太阳电池单片测试仪测试电池性能.发现背面经离子束刻蚀后,单面扩散和双面扩散电池片的并联电阻、开路电压、填充因子和转换效率都有所提高,而串联电阻和短路电流的变化则...     

多晶硅太阳电池背表面刻蚀提升其性能的产线工艺研究

对比研究了产线上多晶硅太阳电池背表面刻蚀对 其光电转换性能的影响。示范性实验结果表明:多晶硅太阳电池背表面刻蚀能够改善其短路 电流, 从而相应的光电转换效 率提升了约 0．1％。依据多晶硅太阳电池背表面刻蚀前后的扫描 电镜(SEM)形貌、背表面漫 反射光谱及完整电池片外量子效率的测试结果,改进的光电转换的原因可能源于背表面刻蚀 “镜面”化有利于太阳光子在背表面内反射和改进印刷Al浆与背表面覆盖接触。背表面刻蚀 与当前晶硅电池产线工艺兼容,能够提升电池片的光电转换效率,是一种可供选择的产线升 级工艺。     

离子束刻蚀碲镉汞的沟槽深宽比改进

高深宽比离子束刻蚀技术是实现碲镉汞红外焦平面探测器的关键工艺技术.国内应用最广泛的双栅考夫曼刻蚀机束散角较大,沟槽深宽比较低.针对Ar离子束刻蚀机,尝试了三种提高深宽比的方法:选择不同的光刻胶做掩模、改变刻蚀角度和使用三栅离子源,并通过扫描电子显微镜(SEM)观察了碲镉汞刻蚀图形的剖面轮廓并计算了深宽比.分析了这些工艺方法对刻蚀图形轮廓的影响,获得了一些有助于获得高深宽比的离子束刻蚀沟槽的实验结果.     

基于LabVIEW可编程电化学脉冲湿法刻蚀系统设计

针对电化学湿法刻蚀硅微加工需求,基于LabVIEW软件开发平台,利用上位机、可编程直流稳压电源PSM-6003、低温控制和LED光辐照等设备搭建了一种新型可编程电化学湿法刻蚀装置.其中基于LabVIEW的PSM-6003上位机控制软件,可以通过图形界面对系统各种参数实时设置,例如刻蚀电压幅值、刻蚀脉冲频率和占空比、刻蚀电流和刻蚀时间以及刻蚀系统的辅助光照和环境温度等,系统各参数监控和动作执行主要利用美国NI公司PCI-6221数据卡实现.该系统成本低、操作简便、可模块化安装,对促进实验室电化学湿法刻蚀微加工设备的研制有重要借鉴意义.     

反应离子刻蚀PMMA的各向异性刻蚀研究

研究目的是优化Ni掩膜PMMA RIE的刻蚀参数，在氧刻蚀气体中加入表面钝化性气体CHF3，以较快的刻蚀速率获得垂直的侧壁和最小的掩模钻蚀。采用平行板结构的反应离子刻蚀机刻蚀，研究了刻蚀气压，CHF3/O2比率和刻蚀温度对垂直、侧向刻蚀速率和PMMA微结构形貌的影响。试验表明：当CHF3含量大于50%或O2工作气压较低时，会显著影响RV/RL比，当RV/RL比大于8时，试样呈现出完全各向异性刻蚀。     

低功率刻蚀工艺均匀度研究

在二氧化硅刻蚀工艺中,有时为了控制氧化膜的损伤,需要采用低功率刻蚀工艺。文中研究了在低射频功率条件下,通过改变磁场强度、暖机条件及反应气体的组成,对刻蚀均匀度的影响。实验结果表明,在低功率条件下,改变磁场强度和暖机条件对刻蚀均匀度的改变有限,但当向主刻蚀气体中加入氧气后,能较大程度地改变刻蚀均匀度。     

微波等离子体刻蚀技术研究

以Corial 200M型干法刻蚀机的三种刻蚀模式为基础,分析了微波等离子体刻蚀技术的优缺点．并讨论了下电极结构对干法刻蚀形貌、一致性和重复性的影响。利用微波等离子体刻蚀技术与反应离子刻蚀技术相结合,实现了SiO2各向同性刻蚀,成功应用于质量控制和失效分析等环节。     

基于OES的等离子体刻蚀过程

光学发射光谱(OES)诊断技术是高密度等离子体刻蚀工艺过程的关键技术,OES信号作为一种实时信号可以用来预测刻蚀过程的进展程度和判断刻蚀性能的好坏.在自行研发的等离子体刻蚀机平台上,采用美国海洋公司的OES传感器系统,采集多晶硅刻蚀工艺中所产生的OES信号,利用主元素分析法(PCA)对OES数据进行压缩处理,提高了实时信号的快速处理能力.对实验数据的分析表明:波长为405 mn的OES谱线可以明确显示出等离子体刻蚀进程,是一条表征等离子体刻蚀过程的状态检测及终点检测控制的特征谱线.在此基础之上,提出了基于PCA法的终点检测算法,用以判断刻蚀终点.     

Depletion m.o.s. power transistors

A new depletion m.o.s. transistor is proposed. The structure uses anisotropic etching to define the channel in an n?p epitaxial silicon slice. The fabrication, characteristics and power capabilities of the device are discussed.     

A general simulator for VLSI lithography and etching processes: Part II—Application to deposition and etching

The extension of the general process simulator SAMPLE to plasma etching and metallization is described. The etching algorithm is divided into isotropic, anisotropic, and direct milling components and is suitable for modeling wet etching, plasma etching, reactive ion etching, and ion milling. Separate deposition algorithms are used for CVD, sputtering, and planetary deposition. With the extension, it is possible to use a simple keyword repertoire to simulate a sequence of photolithography, etching, and deposition steps to obtain device cross sections at each stage of fabrication.     

Microline-etching technique

This paper describes a technique of etching composite layers of molybdenum + gold into lines of micron dimensions. The technique makes use of sputter etching the composite layer of gold + molybdenum using the photo-resist as the mask and then using the chemical etching method to selectively etch the under layer of molybdenum. As a result, it is possible to under-cut the molybdenum film in a controllable manner thereby achieving lines of micron dimensions while leaving a wide and thick gold layer on the top. The various advantages of the technique are also pointed out.     

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.     

氮化硅薄膜的等离子干法蚀刻

本文简述了干法腐蚀的现状、原理及其反应装置.给出了在圆筒型反应器中氮化硅薄膜的均匀刻蚀以及硅表面的平滑抛光的工艺条件,同时,也给出了在此工艺条件下,单晶硅、氮化硅、热生长二氧化硅、砷化镓以及光致抗蚀剂的腐蚀速率.对硅表面在高频场和等离子体轰击下表面性质的改变作了初步研究.并通过此工艺在制管中的成功应用,可看到它在降低成本,减少公害,以及进行微细加工方面所显示出来的优越性.目前,对实验结果和现象的分析尚处于定性的阶段.     

蓄电池鼓包检测传感器的设计与实现

为了实现蓄电池鼓包检测,蓄电池鼓包检测传感器采用压力检测方法将传感器紧贴在被检测蓄电池表面,实现对6V/12V蓄电池鼓包状态365d×24h实时检测,并将检测结果实时显示在上位机监测系统中。实验结果表明：蓄电池鼓包检测传感器与现有的人工巡检方式相比,能够检测到蓄电池细微的鼓包,准确度达到98%以上,同时实现了实时在线监测。因此,蓄电池鼓包检测传感器能够促进对各个领域上蓄电池使用的科学性,延长蓄电池使用寿命。     

准分子激光电化学刻蚀硅的刻蚀质量研究

为了解决现有硅刻蚀工艺中存在的刻蚀质量等问题,采用激光加工技术和电化学加工技术相结合的工艺对硅进行了刻蚀,研究了该复合工艺的工艺特性。实验中采用248nm-KrF准分子激光作光源聚焦照射浸在KOH溶液中的阳极n-Si上,实现激光诱导电化学刻蚀。在实验的基础上,研究了激光电化学刻蚀Si的刻蚀孔的基本形貌,并对横向刻蚀和背面冲击等质量问题进行了分析。结果表明,该工艺刻蚀的孔表面质量好、垂直度高;解决了碱液中Si各向异性刻蚀的自停止问题,具有加工大深宽比微结构的能力;也具有不需光刻显影就能进行图形加工的优越性。     

Depletion V-groove MOS (VMOS) power transistors

A new depletion MOS transistor is proposed. The structure uses anisotropic etching to define the channel in an n/p epitaxial silicon slice. A simple planar model is developed to explain the characteristics of the devices and is verified by measurements on experimental structures.Power devices are fabricated to illustrate the power capability of the structure. Parameters measured for this structure include: junction temperature, d.c. power dissipation, distortion, ac output power, efficiency. The devices were found to be capable of delivering up to 12W with a cutoff frequency of 80 MHz.     

基于各向同性干法刻蚀的大面积悬空Al膜制备

热声传感器随着多孔硅的热致超声发射现象的发现越来越受到关注。热声传感器通过改变器件表面热量而在周围空气中产生交变压力,从而向外发出声波。热声传感器的关键器件是悬空金属薄膜。制备大面积悬空薄膜释放有一定的难度,需要考虑金属薄膜本身的应力与粘附效应。该文提出了两种基于各向同性干法刻蚀的制备金属薄膜的方法,利用XeF2/SF6制备悬空Al膜。由于XeF2与SF6气体刻蚀硅时对于Al有较高的选择比,XeF2对于硅是各向同性刻蚀且有很高的刻蚀速率,而通过设置感应耦合等离子体（ICP）刻蚀机的参数也可利用SF6达到各向同性刻蚀。基于上述特点制备了悬空Al膜,设计相应的制备流程,探索XeF2刻蚀机与ICP刻蚀机合适的刻蚀参数。所制备的悬空Al膜平整、无杂质,具有良好的形貌。     

Reactive ion etching for VLSI

Reactive Ion Etching (RIE) is a dry etching technique that is used to etch 1-µm and submicrometer patterns into films of silicon and silicon compounds. RIE is suitable for VLSI applications because etching is anisotropic and proceeds via chemical reactions with the substrate. Anisotropic etching allows faithful reproduction of resist patterns into the films that make up a device, and chemical etching allows development of selective etching by manipulating the composition of the plasma. The RIE reactor is described and examples of its use to fabricate 1-µm MOSFET's are given. Concerns arising from the presence of a voltage between the substrates and the plasma, radiation damage of SiO2and contamination of silicon, are discussed.