Short channel models and scaling limits of SOI and bulk MOSFETs

Analytical device-physics-based models for subthreshold drain current in short channel SOI MOSFETs facilitate accurate and efficient circuit simulation. These models also enable prediction of device scaling limits determined by subthreshold conduction and comparison of these limits with bulk MOSFETs for the same threshold and supply voltages     

Modeling of subthreshold characteristics for undoped and doped deep nanoscale short channel double-gate MOSFETs

A model of subthreshold characteristics for both undoped and doped double-gate (DG) MOSFETs has been proposed. The models were developed based on solution of 2-D Poisson's equation using variable separation technique. Without any fitting parameters, our proposed models can exactly reflect the degraded subthreshold characteristics due to nanoscale channel length. Also, design parameters such as body thickness, gate oxide thickness and body doping concentrations can be directly reflected from our models. The models have been verified by comparing with device simulations' results and found very good agreement.     

Measuring the effective channel length of MOSFETs

Eleven measurement methods are outlined, and their assumptions are examined. The methods are analyzed, critiqued, and compared. Recommendations are made as to which methods are best under various conditions     

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500°C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1×10¹⁷ cm^-3, the optimum depth was found to be 0.2 μm. Under this condition, a channel mobility of 140 cm²/Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide     

High-current snapback characteristics of MOSFETs

The high-current snapback characteristics of MOSFETs with different channel lengths and widths, gate oxide thicknesses, and substrate dopings were studied to determine their effectiveness in electrostatic discharge stress protection. Filamentary conduction was not observed for currents up to 7 mA/μm of channel width for a pulsewidth of 500 ns. MOSFETs with shorter channel lengths require lower voltages to sustain the same current, independent of gate oxide thickness. Increasing the substrate doping does not necessarily reduce the high current voltage. These trends can be explained using a simple lateral n-p-n bipolar transistor snapback model     

p-channel germanium MOSFETs with high channel mobility

The fabrication and performance of p-channel germanium MOSFETs having a nitrided native oxide gate insulator are reported. A self-aligned dummy-gate process suitable for circuit integration is utilized. Common-source characteristics exhibit no looping and indicate a peak room-temperature channel mobility of 770 cm²/V-s. These results provide further evidence that a high-performance germanium CMOS technology is possible     

Separation of channel backscattering coefficients in nanoscale MOSFETs

Channel backscattering coefficients in the k/sub B/T layer (near the source) of 1.65-nm-thick gate oxide, 68-nm gate length bulk n-channel MOSFETs are systematically separated into two distinct components: the quasithermal-equilibrium mean-free-path for backscattering and the width of the k/sub B/T layer. Evidence to confirm the validity of the separation procedure is further produced: 1) the near-source channel conduction-band profile; 2) the existing value of k/sub B/T layer width from the sophisticated device simulation; and 3) an analytic temperature-dependent drain current model for the channel backscattering coefficients. The findings are also consistent with each other and therefore corroborate channel backscattering as the origin of the coefficients. Other interpretations and clarifications are determined with respect to the very recently released Monte Carlo particle simulation. Consequently, it can be reasonably claimed that the separated components, as well as their dependencies on temperature and bias, are adequate while being used to describe the operation of the devices undertaken within the framework of the channel backscattering theory.     

短沟道三材料柱状围栅MOSFET的解析模型

在柱坐标系下利用电势的抛物线近似,求解二维泊松方程得到了短沟道三材料柱状围栅金属氧化物半导体场效应管的中心及表面电势。推导了器件阈值电压、亚阈值区电流和亚阈值摆幅的解析模型,分析了沟道直径、栅氧化层厚度和三栅长度比对阈值电压、亚阈值区电流和亚阈值摆幅的影响。利用Atlas对具有不同结构参数的器件进行了模拟研究和比较分析。结果表明,基于解析模型得到的计算值与模拟值一致,验证了所建模型的准确性,为设计和应用此类新型器件提供了理论基础。     

短沟道MOST阈值电压温度系数的分析

本文分析了短沟道ＭＯＳＴ阈值电压在室温以上的温度特性，并给出了它的温度系数计算公式。根据计算结果，可以得到如下结论：短沟道ＭＯＳＴ的阈值电压温度系数随着沟道长度缩短而减小．与长沟道ＭＯＳＴ相似，在一定的温区范围内，可以把短沟道ＭＯＳＴ的阈值电压温度系数作为常数，用线性展开式来表达阈值电压的温度特性。     

Hot electron noise effects in buried channel MOSFETs

Measurements are reported on a 2.0 μmeter buried channel MOSFET. Because of the short channel length, the device showed large hot electron effects. The noise reaches a limiting value above a few MHz; this is attributed to hot electron thermal noise. The parameter $\text{α = (}\text{q}\text{2kT}\text{)(}\text{I}{}_{\mathrm{eq}}\text{g}{}_{\mathrm{m}}\text{)}$ is plotted as a function of the absolute temperature T; it increases with decreasing temperature, as expected for hot electron effects.     

A channel resistance derivative method for effective channel lengthextraction in LDD MOSFETs

A channel resistance derivative method for extracting the electrical effective channel length and series resistance is proposed, and demonstrated on an advanced 0.35 μm LDD CMOS technology. A clear graphic image of the L_EFF and R_SD is obtained directly from the measured channel resistance and its derivative with respect to the gate bias. The method also provides guidelines for the proper gate bias range selection in traditional L_EFF extraction techniques     

Power aware channel width tapering of serially connected MOSFETs

This paper reviews a transistor channel width tapering scheme called Hill Tapering for FET chains with specific emphasis on power dissipation and layout area of the tapered chains. The Hill Tapering scheme results in the lowest power dissipation and physical area compared to any of the existing tapering schemes like linear, exponential or optimal tapering. It also offers high speed operation. This tapering scheme is general and suits domino logic circuit designs. SPICE simulation results have shown that up to 81% power dissipation reduction could be achieved by using this tapering scheme.     

Analytical modeling of MOSFETs channel noise and noise parameters

Simple analytical expressions for MOSFETs noise parameters are developed and experimentally verified. The expressions are based on analytical modeling of MOSFETs channel noise, are explicit functions of MOSFETs geometry and biasing conditions, and hence are useful for circuit design purposes. Good agreement between calculated and measured data is demonstrated. Moreover, it is shown that including induced gate noise in the modeling of MOSFETs noise parameters causes /spl sim/5% improvement in the accuracy of the simple expressions presented here, but at the expense of complicating the expressions.     

Short channel epi-MOSFET model

We show how threshold voltages and the electric field perpendicular to a channel are controlled by varying the thickness of the epi-layer in long epitaxial channel MOSFET devices (epi-MOSFETs). Using our proposal of a two-region polynomial potential distribution and a universal boundary condition that effectively expresses the variation of depletion width along a channel, we calculated the two-dimensional (2-D) potential distribution. We also derived a threshold voltage model for short channel epi-MOSFETs. Our model reproduces the numerical data of sub-0.1-/spl mu/m gate length devices, and predicts that the short channel immunity of these devices is not as good as predicted by the previous model. However, their performance is superior to that of double-gate SOI MOSFETs.     

Sub-threshold behavior of long channel undoped cylindrical surrounding-gate MOSFETs

This paper reported the sub-threshold behavior of long channel undoped surrounding-gate (SRG) MOSFETs with respect to body radius. Based on a rigorous channel potential model presented in this work, the ideal room temperature subthreshold slope of 60 mV/dec can only be achieved when the silicon body radius is smaller than a critical value. With larger silicon body radius, SRG MOSFETs display a dual subthreshold slope of 60 mV/dec and 120 mV/dec. Based on the complex subthreshold characteristics, a new definition of threshold voltage together with an extraction method is adopted to investigate threshold voltage characteristics of undoped SRG MOSFETs in this paper.     

短沟道MOSFET本征电容模型的研究

<正> 一、引言 随着MOS集成电路向短沟道、高速化发展,MOS晶体管电容对电路性能的影响更为突出。对电路性能影响较大的栅—漏,栅—源本征电容C_(GD),C_(GS)与长沟器件的主要不同是:(1)饱和区C_(GD)≠0,随着沟道缩短,C_(GD)占总本征栅电容的比例增大。(2)C_(GD)由饱和区到线性区呈平缓过渡状。(3)饱和区C_(GS)减小,并由次开启到饱和区的上升趋势变缓。分析表明,栅电容的短沟效应与沟长调制和速度饱和迁移率有关。     

Electrical characteristics of MOSFETs using low-pressurechemical-vapor-deposited oxide

The electrical characteristics of MOSFETs and MOS capacitors utilizing thin (80-230 Å) low-pressure chemical-vapor-deposited (LPCVD) oxide films deposited at 12 Å/min are presented. MOSFETs using CVD oxides show good electrical characteristics with 70-90% of the surface mobility of conventional MOSFETs. The CVD oxides exhibit the same low leakage current and high breakdown fields as the thermal oxides, and significantly lower trapping and trap generation rates than thermally grown oxides. Interface state densities of ⩽3×10¹⁰ cm^-2 eV^-1 are obtained from CVD devices by using a short annealing in oxygen ambient following the deposition. These results indicate that these LPCVD oxide films may be promising dielectrics for MOS device application     

On the drain current saturation in short channel MOSFETs

Submicron MOSFETs are the issue for ULSI integrated circuits. However, drastic reduction of device size leads to a complex modeling of the MOSFET drain current, which is affected by the electrical and physical phenomena induced by the low device dimension. Several current models are proposed to explain the drain current behavior in the saturation region of the I_D-V_D characteristic curve. Mainly, we can distinguish two types: long channel and short channel current modeling. In the present work, a survey of current voltage models is presented aiming a contribution to the interpretation of the current behavior in the saturation region of the I-V curves, i.e. non-saturation of the drain current, which are critical in submicronic devices.     

Analytical threshold voltage model for short channel double-gateSOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation and assuming the minimum potential determines the threshold voltage, V_th, we derived a model for V_th of short channel double-gate SOI MOSFETs, and verified its validity by comparing with numerical data. We evaluated the threshold voltage lowering, ΔV_th, and subthreshold swing (S-swing) degradation with decreasing gate length L _G, and showed that we can design a 0.05-μm-L_G device with ΔV_th of less than 50 mV and an S-swing of less than 70 mV/decade if 10-nm-thick SOI is available     

Reduced floating body effects in narrow channel SOI MOSFETs

An experimental demonstration is given of the reduction of floating body effects in narrow channel SOI MOSFETs, as manifested by the saturation region subthreshold characteristics, latch-up, and breakdown voltage. The mechanisms responsible for this reduction are explained by original experiments and simulations. These are a deterioration of the carrier lifetime near the channel edges caused by local stress and defects, and a lowering of the source-body built-in potential barrier, resulting from dopant outdiffusion/segregation into the isolation oxide