Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz60 MHz low noise amplifier (LNA) designed in a 0.35 m SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure (NF) of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point (IP1dB) of ?11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.     

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.     

一种S波段平衡式限幅低噪声放大器的设计

介绍了一种小型化平衡式限幅低噪声放大器。该放大器采用Lange桥平衡结构,在实现低噪声的同时,保证了小电压驻波比;在3.0～3.5GHz频带内,噪声系数小于1.3dB,输入输出驻波系数小于1.3,增益大于27dB,平坦度±0.6dB以内,输出1dB压缩点大于12dBm。该放大器能够承受最大5W的连续波功率输入,且大功率输入时的驻波系数小于1.3。     

A fully integrated SOC for 802.11b in 0.18-/spl mu/m CMOS

A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.     

A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver forwireless applications

A 2.2-V operation, single-chip GaAs MMIC transceiver has been successfully developed for 2.4-GHz-band wireless applications such as wireless local area network terminals. The chip is fabricated using a planar self-aligned gate field-effect transistor. To generate sufficient negative voltage for gate-biasing and to enhance switch power handling capability under a 2.2-V supply, a newly designed negative voltage generator with a voltage doubler (NVG-VD) and a switch control logic circuit are integrated on the chip, together with a power amplifier, a transmit/receive switch, and a low-noise amplifier. The NVG-VD is designed to produce both a 3.3-V positive step-up voltage and a -2.1-V negative voltage under 2.2 V in operation voltage. Biased with these outputs, the logic circuit accommodates high power outputs of over 25 dBm with a low operating voltage of 2.2 V in transmit mode, With a 2.45-GHz modulated signal based on IS-95 standards, a 21-dBm output power and a 33% efficiency are obtained at a ±1.25-MHz-offset adjacent channel power rejection of -45 dBc. In receive mode, a low-noise amplifier achieves a 1.8-dB noise figure and an 11-dB gain with a 3.0-mA current. This transceiver enables significant size and weight reductions in 2.4-GHz-band wireless application terminals     

应用于无线传感器网络低噪声放大器的设计

本文给出一种应用于无线传感器网络射频前端低噪声放大器的设计,采用SMIC0．18μmCMOS工艺模型。在CadenceSpectre仿真环境下的仿真结果表明：该低噪声放大器满足射频前端的系统要求,在2．45GHz的中心频率下增益可调,高增益时,噪声系数为2．9dB,输入P1dB压缩点为-19．8dBm,增益为20．5dB;中增益时,噪声系数为3．6dB,输入P1dB压缩点为-15．8dBm,增益为12．5dB;低增益时,噪声系数为6．0dB,输入P1dB压缩点为-16．4dB,增益为2．2dB。电路的输入输出匹配良好,在电源电压1．8V条件下,工作电流约为6mA。     

80-GHz Tuned Amplifier in Bulk CMOS

An 80-GHz six-stage common source tuned amplifier has been demonstrated using low leakage (higher V_T) NMOS transistors of a 65-nm digital CMOS process with six metal levels. It achieves power gain of 12 dB at 80 GHz with a 3-dB bandwidth of 6 GHz, noise figures (NF's) lower than 10.5 dB at frequencies between 75 and 81 GHz with the lowest NF of 9 dB. IP_{1 dB} is -21 dBm and IIP3 is -11.5 dBm. The amplifier consumes 27 mA from a 1.2 V supply. At V_DD = 1.5 V and 33 mA bias current, NF is less than 9.5 dB within the 3-dB bandwidth and reaches a minimum of 8 dB at 80 GHz.     

毫米波大动态宽带单片低噪声放大器

利用0.25μmGaAsPHEMT低噪声工艺,设计并制造了2种毫米波大动态宽带单片低噪声放大器。第1种为低增益大动态低噪声放大器,单电源+5V工作,测得在26～40GHz范围内,增益G=10±0.5dB,噪声系数NF≤2.2dB,1分贝压缩点输出功率P1dB≥15dBm;第2种为低压大动态低噪声放大器,工作电压为3.6V,静态电流0.6A(输出功率饱和时,动态直流电流约为0.9A),在28～35GHz范围内,测得增益G=14～17dB,噪声系数约4.0dB,1分贝压缩点输出功率P1dB≥24.5dBm,最大饱和输出功率≥26.8dBm,附加效率约10%～13.6%。结果中还给出了2种放大器直接级联的情况。     

一种自适应线性化偏置的单片集成功率放大器

提出一种自适应线性化偏置的电路结构,通过调节控制电压改变偏置管的工作状态,提高功率放大电路的线性度,降低偏置电流对参考电压和环境温度的敏感度.利用双反馈环结构抑制输入阻抗随频率的变化,实现了宽带匹配,拓展了放大器的带宽.采用微波电路仿真软件AWR进行仿真,验证了带宽范围内的相位偏离度在2°以内.基于2μm InGaP/GaAs HBT工艺,设计了集成电路版图并成功流片.测试结果表明:在3.5V电压供电下,该放大器在1～2.5 GHz频带范围内,输入反射系数均在-10 dB以下,功率增益为23 dB,输出功率大于30 dBm,误差向量幅度在2.412 GHz时为.2.7％@24 dBm,最大功率附加效率达40％.     

3．1～10．6GHz超宽带低噪声放大器的设计

基于SIMC0．18μmRFCMOS工艺技术,设计了可用于3．1—10．6GHzMB—OFDM超宽带接收机射频前端的CMOS低噪声放大器（LNA）。该LNA采用三级结构：第一级是共栅放大器,主要用来进行输入端的匹配;第二级是共源共栅放大器,用来在低频段提供较高的增益;第三级依然为共源共栅结构,用来在高频段提供较高的增益,从而补偿整个频带的增益使得增益平坦度更好。仿真结果表明：在电源电压为1．8v的条件下,所设计的LNA在3．1～10．6GHz的频带范围内增益（521）为20dB左右,具有很好的增益平坦性f±0．4dB）,回波损耗S11、S22均小于-10dB,噪声系数为4．5dB左右,IIP3为-5dBm,PIdB为0dBm。     

一种5~6 GHz宽带全集成CMOS低噪声放大器

采用55 nm标准CMOS工艺,设计并流片实现了一种应用于Wi-Fi 6(5 GHz)频段的宽带全集成CMOS低噪声放大器(LNA)芯片,包括源极退化共源共栅放大器、负载Balun及增益切换单元。在该设计中,所有电感均为片上实现;采用Balun负载,实现信号的单端转差分输出;具备高低增益模式,以满足输入信号动态范围要求。测试结果表明,在高增益模式下该放大器的最大电压增益为20.2 dB,最小噪声系数为2.2 dB;在低增益模式下该放大器的最大电压增益为15 dB,最大输入1 dB压缩点为-3.2 dBm。芯片核心面积为0.28 mm²,静态功耗为10.2 mW。     

Millileter-Wave Power-Combining Amplifier Using A Broadband Waveguide Combiner

A Millimeter-wave power-combining amplifier based on the multi-way rectangular-waveguide power-dividing/combining circuit has been presented and investigated. The equivalent-circuit approach has been used to analyze the passive power-dividing/combining circuits. An eight-device amplifier is designed and measured to validate the power-dividing/combining mechanism using this technique. Both the measured 10-dB return loss bandwidth and the 2-dB insertion loss bandwidth of the passive system are more than 10?GHz. The measured maximum small-signal gain of the millimeter-wave eight-device power amplifier is 22.5?dB at 26.8?GHz with a 3-dB bandwidth of more than 6?GHz, while the input and output return loss of the proposed eight-device power amplifier is around ?10?dB from 26?GHz to 36?GHz. The measured maximum output power at 1-dB compression from the power amplifier is 28 dBm at 29.5?GHz.     

A Parallel Power Amplifier With a Novel Mode Switching Control

Two parallel operating power amplifiers (PAs) are controlled by a novel mode switch for high efficiencies at both the back-off power region and high power region. The mode switch is realized by the base-collector (BC) junction diode which reuses the dc current of the low power mode amplifier. A 836 MHz CDMA PA has been demonstrated using InGaP/GaAs heterojunction bipolar transistor with fully integrated matching component for small package and low cost. It shows a 13 mA idle current, 15.4% power added efficiency (PAE), ACPR1 at 16 dBm of the low power mode operation and a 40.5% PAE, ACPR1 at 28 dBm of the high power mode operation.     

A Two-Stage IMPATT-Diode Amplifier

The system aspects and packaging of a two-stage FM IMPATT-diode amplifier are described. The amplifier combines the output power of 4 IMPATT diodes in the final stage to provide an output power of greater than 4 W at 6 GHz. The system has a locking bandwidth of greater than 200 MHz with a 16-dB gain and a noise figure of less than 50 dB. Both the design and the experimental performance of the amplifier and each of its stages are discussed. The noise characterization of IMPATT-diode amplifiers, operating as injection-locked oscillators or stable amplifiers, determined the mode of operation for each stage. Included in the paper are experimental results of large-signal noise characterization of both Si and GaAs IMPATT diodes, as are the noise characteristics related to the output power and gain.     

A novel amplifying antenna array using patch-antenna couplers-design and measurement

This paper proposes a novel amplifying antenna array using the patch-antenna coupler formed by placing one or two open-ended microstrip lines (coupled lines) near and along the nonradiating edge(s) of a patch antenna. An X-band five-element array with broadside 25-dB Chebyshev radiation is demonstrated. When the input signal is fed to the center element, with most of the power radiating from the antenna, part of it is tapped to the coupled lines, amplified by an FET amplifier, and fed to the next antenna element. This process is repeated after all the antenna elements are fed with suitable power. The amplitude distribution of the fields radiated from the antennas is controlled by the coupling coefficient from the patch to the coupled line, which, in turn, is governed by the coupling length and gap between the patch and line. The measured return loss of the designed five-element array is -27 dB at the center frequency of 10 GHz with 2% 10-dB bandwidth. The radiation pattern possesses a transmitting gain of 15.9 dB, a half-power beamwidth of 17/spl deg/, and a sidelobe level of -22 dB.     

Design and Performance of Microwave Amplifiers with GaAs Schottky-Gate Field-Effect Transistors

The design and performance of an X-band amplifier with GaAs Schottky-gate field-effect transistors are described. The amplifier achieves 20 /spl plusmn/ 1.3-dB gain with a 5.5-dB typical noise figure (6.9 dB maximum) over the frequency range of 8.0-12.0 GHz. The VSWR at the input and output ports does not exceed 2.5:1. The minimum output power for 1-dB gain compression is +13 dBm, and the intercept point for third-order intermodulation products is +26 dBm. The design of practical wide-band coupling networks is discussed. These networks minimize the overall amplifier noise figure and maintain a constant gain in the band.     

1.3μm高增益偏振无关应变量子阱半导体光放大器

采用低压金属有机化学气相外延法 (LP MOVPE)生长并制作了 1 3μm脊型波导结构偏振无关半导体光放大器 (SOA) ,有源区为基于四个压应变量子阱和三个张应变量子阱交替生长的混合应变量子阱 (4C3T)结构 ,压应变阱宽为 6nm ,应变量 1 0 % ,张应变阱宽为 11nm ,应变量 - 0 95 % ;器件制作成 7°斜腔结构以有效抑制腔面反射。半导体光放大器腔面蒸镀Ti3 O5/Al2 O3 减反 (AR)膜以进一步降低腔面剩余反射率至 3× 10 -4以下 ;在 2 0 0mA驱动电流下 ,光放大器放大的自发辐射 (ASE)谱的 3dB带宽大于 5 0nm ,光谱波动小于 0 4dB ,半导体光放大器管芯的小信号增益近 30dB ,在 12 80～ 1340nm波长范围内偏振灵敏度小于 0 6dB ,饱和输出功率大于 10dBm ,噪声指数 (NF)为 7 5dB。     

High-power Er-Yb-doped fiber amplifier with multichannel gain flatness within 0.2 dB over 14 nm

A high-power Er-Yb fiber amplifier for WDM applications has been constructed using a matched mid-stage gain shaping filter. Using precise measurements and careful design considerations, excellent gain flatness, with less than 0.2-dB variation, was obtained over a 14-nm spectral bandwidth. By simply adjusting the pump power to the amplifier, it was possible to maintain the flattened amplifier gain shape over a wide input signal power range from -11 dBm to 1 dBm. A low external noise figure of 5.2 dB at 1-dBm signal input and a high-output power up to 24.6 dBm has been measured.     

一种偏置电流可调节的高效率2.4GHz锗硅功率放大器

基于IBM0.35μm SiGe BiCMOS工艺BiCMOS5PAe实现了一种偏置电流可调节的高效率2.4GHz锗硅功率放大器。该功率放大器采用两级单端结构和一种新型偏置电路,除射频扼流电感外,其它元件均片内集成。采用的新型偏置电路用于调节功率放大器的静态偏置电流,使功率放大器工作在高功率模式状态或低功率模式状态。在3.5V电源条件下,功率放大器在低功率模式下工作时,与工作在高功率模式下相比,其功率附加效率在输出0dBm时提高了56.7%,在输出20dBm时提高了19.2%。芯片的尺寸为1.32mm×1.37mm。     

5-GHz CMOS radio transceiver front-end chipset

Incorporating the direct-conversion architecture, a 5-GHz band radio transceiver front end chipset for wireless LAN applications is implemented in a 0.25-μm CMOS technology. The 4-mm² 5.25-GHz receiver IC contains a low noise amplifier with 2.5-dB noise figure (NF) and 16-dB power gain, a receive mixer with 12.0 dB single sideband NF, 13.7-dB voltage gain, and -5 dBm input 1-dB compression point. The 2.7-mm² transmitter IC achieves an output 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4-dB (image) sideband rejection by using an integrated quadrature voltage-controlled oscillator. Operating from a 3-V supply, the power consumptions for the receiver and transmitter are 114 and 120 mW, respectively