Performance assessment of (1 1 0) p-FET high-κ/MG: is it mobility or series resistance limited?

In this article the impact of Si-substrate orientation on mobility performance is studied for p-MOSFET’s with both HfSiON and SiON based dielectrics. Consistent with previous studies, the I_on at fixed I_off is 100% larger for Si(1 1 0) larger than for standard Si(1 0 0). A thorough analysis of the factors influencing I_on (EOT, mobility and R_series) for short channel devices (until L_met = 80 nm) indicates that a 200% increase of the mobility at high V_g is the source of this performance enhancement. The lower I_on increase (only 100%) compared to what is expected from the mobility is only explained by a larger impact of the R_series (70% of the total resistance) for short channel devices. As a result additional room for I_on improvement can be reached by device and R_series optimization.     

IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures

Thin film transistors (TFTs) with bottom gate and staggered electrodes using atomic layer deposited Al₂O₃ as gate insulator and radio frequency sputtered In–Ga–Zn Oxide (IGZO) as channel layer are fabricated in this work. The performances of IGZO TFTs with different deposition temperature of Al₂O₃ are investigated and compared. The experiment results show that the Al₂O₃ deposition temperature play an important role in the field effect mobility, I_on/I_off ratio, sub-threshold swing and bias stability of the devices. The TFT with a 250 °C Al₂O₃ gate insulator shows the best performance; specifically, field effect mobility of 6.3 cm²/Vs, threshold voltage of 5.1 V, I_on/I_off ratio of 4×10⁷, and sub-threshold swing of 0.56 V/dec. The 250 °C Al₂O₃ insulator based device also shows a substantially smaller threshold voltage shift of 1.5 V after a 10 V gate voltage is stressed for 1 h, while the value for the 200, 300 and 350 °C Al₂O₃ insulator based devices are 2.3, 2.6, and 1.64 V, respectively.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Solution-processed single-crystal perylene diimide transistors with high electron mobility

We have successfully demonstrated a single-crystal field-effect transistors (FETs) based on an asymmetric perylenetetracarboxylic diimide (a-PDI) compound with polystyrene (PS)/SiO₂ bilayer as gate dielectric. The single crystals are in-situ grown on substrate from simple solution evaporation method, thus may be suitable for large area electronics applications. The PS modified gate dielectric could minimize charge trapping by the hydroxyl groups of the SiO₂ surface. The resulting solution processed single crystals transistors are characterized in ambient air, and exhibited maximum electron mobility of ca. 1.2 cm² V⁻¹ s⁻¹ and high I_on:I_off > 10⁵.     

Effect of gate insulator thickness on device performance of InGaZnO thin-film transistors

Top-contact thin-film transistors (TFTs) are fabricated in this work using atomic layer deposition (ALD) Al₂O₃ as the gate insulator and radio frequency sputtering InGaZnO (IGZO) as the channel layer so as to investigate the effect of Al₂O₃ thickness on the performance of IGZO-TFTs. The results show that TFT with 100-nm-thick Al₂O₃ (100 nm-Al₂O₃-TFT) exhibits the best electrical performance; specifically, field-effect mobility of 5 cm²/Vs, threshold voltage of 0.95 V, I_on/I_off ratio of 1.1×10⁷ and sub-threshold swing of 0.3 V/dec. The 100 nm-Al₂O₃-TFT also shows a substantially smaller threshold voltage shift of 1.1 V after a 10 V gate voltage is applied for 1 h, while the values for TFTs with an Al₂O₃ thickness of 220 and 280 nm are 1.84 and 2 V, respectively. The best performance of 100 nm-Al₂O₃-TFT can be attributed to the larger capacitance and the smaller amount of total trap centers possessed by a thinner insulator compared to the thicker ones.     

The influence of junction depth on short channel effects in vertical sidewall MOSFETs

This work addresses a fundamental problem of vertical MOSFETs, that is, inherently deep junctions that exacerbate short channel effects (SCEs). Due to the unconventional asymmetric junction depths in vertical MOSFETs, it is necessary to look separately at the electrostatic influence of each junction. In order to suppress short channel effects better, we explore the formation of a shallow drain junction. This is realized by a self-aligned oxide region, or junction stop (JS) which is formed at the pillar top and acts as a diffusion barrier for shallow junction formation. The benefits of using a JS structure in vertical MOSFETs are demonstrated by simulations which show clearly the effect of asymmetric junctions on SCEs and bulk punch-through. A critical point is identified, where control of SCEs by junction depth is lost and this leads to appropriate junction design in JS vertical sidewall MOSFETs. For a 70 nm channel length the JS structure improves charge sharing by 54 mV and DIBL by 46 mV. For body dopings of 5.0 × 10¹⁷ cm^?3 and 6.0 × 10¹⁷ cm^?3 the JS gives improvements in I_off of 58.7% and 37.8%, respectively, for a given I_on. The inclusion of a retrograde channel gives a further increase in I_on of 586 μA/μm for a body doping of 4.0 × 10¹⁸ cm^?3.     

ZrO2 insulator modified by a thin Al2O3 film to enhance the performance of InGaZnO thin-film transistor

A high-performance InGaZnO (IGZO) thin-film transistor (TFT) with ZrO₂–Al₂O₃ bilayer gate insulator is fabricated. Compared to IGZO-TFT with ZrO₂ single gate insulator, its electrical characteristics are significantly improved, specifically, enhancement of I_on/I_off ratios by one order of magnitude, increase of the field-effect mobility (from 9.8 to 14 cm²/Vs), reduction of the subthreshold swing from 0.46 to 0.33 V/dec, the maximum density of surface states at the channel-insulator interface decreased from 4.3 × 10¹² to 2.5 × 10¹² cm⁻². The performance enhancements are attributed to the suppression of leakage current, smoother surface morphology, and suppression of charge trapping by using Al₂O₃ films to modify the high-k ZrO₂ dielectric.     

Experimental study on the influence of junction temperature on the relationship between IGBT switching energy loss and device current

Accurate determination of power losses in semiconductor devices is important for optimal design and reliable operation of a power converter. The switching loss is an important component of the total device loss in an insulated-gate bipolar transistor (IGBT) in a voltage source inverter. The objective here is to study experimentally the influence of junction temperature on the turn-on switching energy loss E_on and turn-off switching energy loss E_off. More specifically E_on and E_off are both related to device current I_c; the influence of junction temperature on the relationship between E_on and I_c and that between E_off and I_c is studied. As the operating environmental conditions and load conditions of power converter vary widely, a wide range of junction temperatures between − 35 °C and + 125 °C is considered here. The experimental data enable precise determination of the switching loss in each device in a high-power converter at any practical operating condition. This leads to precise estimation of total device loss and optimal thermal design of the converter. This further helps off-line and/or on-line estimation of device junction temperatures required for study of thermal cycles and reliability.     

High mobility strained Si0.5Ge0.5/SSOI short channel field effect transistors with TiN/GdScO3 gate stack

Short channel p-type metal-oxide-semiconductor field effect transistors (MOSFETs) with GdScO₃ gate dielectric were fabricated on a quantum well strained Si/strained Si_0.5Ge_0.5/strained Si heterostructure on insulator. Amorphous GdScO₃ layers with a dielectric constant of 24 show small hysteresis and low density of interface states. All devices show good performance with a threshold voltage of 0.585 V, commonly used for the present technology nodes, and high I_on/I_off current ratios. We confirm experimentally the theoretical predictions that the drive current and the transconductance of the biaxially strained (1 0 0) devices are weakly dependent on the channel orientation. The transistor’s hole mobility, extracted using split C-V method on long channel devices, indicates an enhancement of 90% (compared to SiO₂/SOI transistors) at low effective field, with a peak value of 265 cm²/V s. The enhancement is however, only 40% at high electrical fields. We demonstrate that the combination of GdScO₃ dielectric and strained SiGe layer is a promising solution for gate-first high mobility short channel p-MOSFETs.     

Single-walled carbon nanotube transistors fabricated by advanced alignment techniques utilizing CVD growth and dielectrophoresis

Single-walled carbon nanotube field effect transistors (SWNT-FETs) are fabricated by two different alignment techniques. The first technique is based on direct synthesis of an aligned SWNTs array on quartz wafer using chemical vapor deposition. The transistor with three SWNTs and atomic layer deposited (ALD) Al₂O₃ gate oxide shows a contact resistance of 280 KΩ, a maximum on-current of ?7 μA, and a high I_on/I_off ratio (>10³). The second technique is based on room temperature self-assembly of SWNT bundles using dielectrophoresis. By applying AC electric fields, we have aligned nanotube bundles between drain and source contact patterns of a transistor at room temperature. Transistors based on twisted bundle of SWNTs show high contact resistance (MΩ range) and low current drive in the order of tens of nA.     

Performance analysis of nanoscale GeSn MOSFETs for mixed-mode circuit applications

Using extensive numerical analysis we investigate the impact of Sn ranging 0–6% in compressively strained GeSn on insulator (GeSnOI) MOSFETs for mixed-mode circuit performance at channel lengths (L_g) ranging 100–20 nm with channel thickness values of 10 and 5 nm. Our results reveal that 10 nm thick Ge_0.94Sn_0.06 channel MOSFETs produce improvement of peak transconductance g_m, peak gain Av, peak cut-off frequency f_T and maximum frequency of oscillations f_max by 80.5%, 18.8%, 83.5% and 81.7%, respectively compared with equivalent GeOI device at L_g =20 nm. Furthermore, such devices exhibit 78.8% increase in ON-current I_ON while yield 44.5% reduction in delay as compared to Ge control devices enabling them attractive for logic applications. Thinning of the channel thickness from 10 to 5 nm increases peak Av, peak transconductance efficiency and reduces output conductance and OFF-current I_OFF while degrading other parameters in all GeSnOI and control Ge devices.     

TiSiOx gate dielectrics produced by reactive sputtering for high performance InGaZnO thin film transistors

High dielectric constant TiSiOx thin films are produced by reactive sputtering under different oxygen partial pressure ratio (P_O2) from 15% to 30%. All the TiSiOx films show an excellent transmittance value of almost 95%. The TiSiOx film has a low leakage current density by optimizing oxygen partial pressure, and the leakage current density of TiSiOx film under P_O2 of 20% is 4.88×10⁻⁷ A/cm² at electrical field strength of 2 MV/cm. Meanwhile, their associated InGaZnO thin-film transistors (IGZO-TFTs) with different P_O2 TiSiOx thin films as gate insulators are fabricated. IGZO-TFTs under P_O2 of 20% shows an optimized electrical performance, and the threshold voltage, sub-threshold swing, field effect mobility and I_on/I_off ratio of this device are 2.22 V, 0.33 V/decade, 29.3 cm²/V s and 5.03×10⁷, respectively. Moreover, the density of states (DOS) is calculated by temperature-dependent field-effect measurement. The enhancements of electrical performance and temperature stability are attributed to better active/insulator interface and smaller DOS.     

Nonvolatile memory performance improvements for solution-processed thin-film transistors with composition-modified In–Zn–Ti–O active channel and ferroelectric copolymer gate insulator

The nonvolatile memory thin-film transistors (M-TFTs) using a solution-processed indium-zinc-titanium oxide (IZTiO) active channel and a poly(vinylidene fluoride-trifluoroethylene) ferroelectric gate insulator were fabricated and characterized to elucidate the relationships between the IZTiO channel composition and the memory performances such as program speed and data retention. The compositions of the spin-coated IZTiO layers were modified with different Ti amounts of 0, 2, 5, and 10 mol%. The carrier concentration of IZTiO channel layer was effectively modulated by the incorporated Ti amounts and the defect densities within the channel were effectively reduced by Ti incorporation. The M-TFT fabricated with IZTiO channel with 2-mol% Ti composition exhibited the best overall device performances, in which the μ_FE, SS, MW, and programmed I_on/off were obtained to be 23.6 cm² V^?1 s^?1, 701 mV/decade, 11.8 V, and 1.2 × 10⁵, respectively. Furthermore, thanks to the suitable amounts of Ti incorporation into the IZO, the improved program speed and data retention properties were successfully confirmed.     

Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes

A technique for modeling the effect of variations in multiple process parameters on circuit delay performance is proposed. The variation in saturation current I_on at the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. The delay of a two-input NAND gate with 65 nm gate length transistors is extensively characterized by mixed-mode simulations, which is then used as a library element. Appropriate templates for the NAND gate library are incorporated in a general purpose circuit simulator SEQUEL. A 4-bit × 4-bit Wallace tree multiplier circuit, consisting of two-input NAND gates is used to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, by generating delay distributions, using an extensive Monte Carlo analysis. The use of linear interpolation and linear superposition is evaluated to study simultaneous variations in two and more process parameters. An analytical model for gate delays, in terms of device drive current I_on, is proposed, which can be used to extend this methodology for a generic technology library with a variety of library elements. The model is validated against Monte Carlo simulations and is shown to have a typical error of less than 0.1% for simultaneous variations in multiple process parameters. The proposed methodology can be used for statistical timing analysis and circuit simulation at the gate level.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

Effect of contact-etch-stop-layer and Si1-xGex channel mechanical properties on nano-scaled short channel NMOSFETs with dummy gate arrays

The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20 nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si_0.75Ge_0.25 alloy channel and a + 3.0 GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100 nm gate width.     

Sputtered oxides used for passivation layers of amorphous InGaZnO thin film transistors

Four sputtered oxide films (SiO₂, Al₂O₃, Y₂O₃ and TiO₂) along with their passivating amorphous InGaZnO thin film transistors (a-IGZO TFTs) were comparatively studied in this paper. The device passivated by an Al₂O₃ thin film showed both satisfactory performance (μ_FE=5.3 cm²/V s, I_on/I_off>10⁷) and stability, as was probably related to smooth surface of Al₂O₃ thin films. Although the performance of the a-IGZO TFTs with a TiO₂ passivation layer was also good enough (μ_FE=3.5 cm²/V s, I_on/I_off>10⁷), apparent V_th shift occurred in positive bias-stress tests due to the abnormal interface state between IGZO and TiO₂ thin films. Sputtered Y₂O₃ was proved no potential for passivation layers of a-IGZO TFTs in this study. Despite unsatisfactory performance of the corresponding a-IGZO TFT devices, sputtered SiO₂ passivation layer might still be preferred for its high deposition rate and excellent transparency which benefit the mass production of flat panel displays, especially active-matrix liquid crystal displays.     

High-resolution transmission electron microscopy study on bipolar resistive switching behavior in TiO2 thin films

We fabricated TiO₂ thin films the by sol–gel process. Successful I–V curves can be obtained in the Cu/TiO₂/ATO structure device in which TiO₂ thin film was calcined at 300 °C. The bipolar resistive switching behavior was observed and the ratio of R_off/R_on can be increased to 10⁴. The switching voltage changes from 4.8 to 3.5 V when the current compliance drops from 10 to 0.1 mA. We also investigated the microstructure by HRTEM technology.     

Challenges and performance limitations of high-k and oxynitride gate dielectrics for 90/65 nm CMOS technology

For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO₂-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node.     

Punch-through impact ionization MOSFET (PIMOS): From device principle to applications

In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied Ω- and tri-gate structures to obtain abrupt switching (3–10 mV/decade) combined with a hysteresis in the I_D(V_DS) and I_D(V_GS) characteristics. The PIMOS device shows an extraordinary temperature stability up to 125 °C. The influence of various parameters on device performance as abrupt switch or memory cell is investigated. Reduction of the electrical channel length, i.e. of gate length and/or substrate doping, reduces the breakdown voltage and hence the DRAM operating voltage, but also increase the I_off. Two architectures for a capacitor-less DRAM cell are demonstrated and evaluated. In addition, a PIMOS n-type hysteretic inverter is demonstrated, which may serve as a 1T SRAM cell.