A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.     

A low-power monolithic CMOS transceiver for 802.11b wireless LANs

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (∑△) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of-3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7×4.2 mm2.     

A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-/spl mu/m CMOS

This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54/spl deg//1.1/spl deg/ for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5dBm and the receiver sensitivity is -75/-74 dBm for 2/5-GHz band for 64QAM at 54 Mb/s.     

A direct-conversion CMOS transceiver for the 802.11a/b/g WLAN standard utilizing a Cartesian feedback transmitter

A fully integrated dual-band transceiver is implemented in 0.18-/spl mu/m CMOS and is compliant with the IEEE 802.11a/b/g standards. The direct-conversion transceiver occupies 12 mm/sup 2/ in a QFN-40 package. A fractional-N synthesizer operates at twice the channel frequency, covering continuously bands from 4.9 to 5.9 GHz, as well as the 2.4-GHz band. The 5- and 2.4-GHz receivers achieve a sensitivity level below -73 dBm in the 54-Mb/s mode and below -93 dBm in the 6-Mb/s mode, while consuming 230 mW. A fast RSSI-channel power-detection system allows to power-down signal processing in the listen mode. The 5- and 2.4-GHz transmitters implement a wideband Cartesian feedback loop for enhanced EVM performances and improved spectrum masks compliance. The transmitters deliver -2-dBm average power with an EVM of 3% in the 54-Mb/s mode while consuming 300 mW.     

一种应用于IEEE 802.11 b/g/n无线局域网收发机的CMOS模拟基带电路

本文提出了一种应用于直接变频无线局域网收发机的模拟基带电路,该电路采用标准的0.13微米CMOS工艺实现,包括了采用有源RC方式实现的接收4阶椭圆低通滤波器、发射3阶切比雪夫低通滤波器、包含直流失调消除伺服环路的接收可变增益放大器及片上输出缓冲器。芯片面积共1.26平方毫米。接收基带链路增益可在-11dB至49dB间以2dB步长调节。相应地,基带接收输入等效噪声电压（IRN）在50 nV/sqrt(Hz) 至30.2 nV/ sqrt(Hz)间变化而带内输入三阶交调（IIP3）在21dBm至-41dBm间变化。接收及发射低通滤波器的转折频率可在5MHz、10MHz及20MHz之间选择以符合包含802.11b/g/n的多种标准的要求。接收基带I、Q两路的增益可在-1.6dB至0.9dB之间以0.1dB的步长分别调节以实现发射IQ增益失调校正。通过采用基于相同积分器的椭圆滤波器综合技术及作用于电容阵列的全局补偿技术,接收滤波器的功耗显著降低。工作于1.2V电源电压时,整个芯片的基带接收及发射链路分别消耗26.8mA及8mA电流。     

An auto-I/Q calibrated CMOS transceiver for 802.11g

The CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with an auto-I/Q calibration function for IEEE 802.11g. The transceiver supports I/Q gain and phase mismatch auto tuning mechanisms at both the transmitting and receiving ends, which are able to reduce the phase mismatch to within 1/spl deg/ and gain mismatch to 0.1dB. Implemented in a 0.25 /spl mu/m CMOS process with 2.7 V supply voltage, the transceiver delivers a 5.1 dB receiver cascade noise figure, 7 dBm transmit, and a 1 dB compression point.     

A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs

This paper describes a radio-frequency receiver targeting spread-spectrum wireless local-area-network applications in the 2.4-GHz band. Based on a direct-conversion architecture, the receiver employs partial channel selection filtering, dc offset removal, and baseband amplification. Fabricated in a 0.6-μm CMOS technology, the receiver achieves a noise figure of 8.3 dB, IP₃ of -9 dBm, IP₂ of +22 dBm, and voltage gain of 34 dB while dissipating 80 mW from a 3-V supply     

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-/spl mu/m CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8/spl deg/ rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm/sup 2/.     

A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.     

应用于802.11b无线局域网的单芯片低功耗CMOS收发机

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta （∑△） fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of -3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7 × 4.2 mm^2.     

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

A World-Band Triple-Mode 802.11a/b/g SOC in 130-nm CMOS

A fully integrated system-on-a-chip (SOC) in 130-nm CMOS technology compliant with world-band 802.11a/b/g is presented. This SOC integrates all blocks including 2.4-GHz/5-GHz RF tranceiver, baseband physical layer (PHY), and the medium access controller (MAC). At 1.8 V, the whole SOC dissipates 144/168 mA in receiving mode and 114/150 mA in transmitting mode for 2.4-GHz/5-GHz-band operations. The measured receiver sensitivity at 2.4 GHz/5 GHz is $-{hbox{77.5}}/-{hbox{74}} hbox{dBm}$ at 54 Mb/s rate, and the transmitter EVM at 54 Mb/s rate is $-{hbox{33}}/-{hbox{30}} {hbox {dB}}$ at an output power of $-{hbox{7}}/-{hbox{8}} hbox{dBm}$. By integrating multiple on-chip LDOs with no off-chip capacitors, this SOC features the capability of being directly supplied by off-chip switching-type DC/DC converter without performance degradation.      

Effectiveness and issues of congestion control in 802.11g wireless LANs

The current paper presents a collection of experimental data portraying the performance achieved in the wireless setting by several TCP-friendly congestion controls recently proposed in literature. This work is partly motivated by the consideration that the majority of the analytical results in this area are validated by simulation, rather than by field tests. Examining these algorithms in real environments can help verify their actual effectiveness over the wireless Internet. To reach such goal, two representative controls among the so-called window-based TCP-friendly schemes have been implemented, namely, the General Additive Increase Multiplicative Decrease (GAIMD) strategy, and the SQuare RooT (SQRT) binomial control; the most representative algorithm among rate-based controls, the TCP Friendly Rate Control (TFRC), has also been considered. Their TCP-fairness and smoothness have been comprehensively evaluated in an IEEE 802.11g Wireless Local Area Network (WLAN). The obtained results show that the GAIMD and SQRT strategies reveal non-negligible scalability and smoothness problems, that markedly limit their performance. It is empirically demonstrated that their “optimal” increase/decrease rules, based on TCP-Reno analytical model, cannot guarantee an adequate performance when GAIMD and SQRT compete with TCP-Sack, a de facto standard for current TCP implementations. TFRC is demonstrated to occasionally behave bewildering: properly tuning one of its congestion control parameters and enhancing the algorithm with a flow-control mechanism result in a definitely fairer share of bandwidth with concurrent TCP flows. Michele Borri received the M.Sc. degree in Computer Engineering from the University of Modena and Reggio Emilia in the academic year 2001–2002 and took a specialisation in Telecommunication Engineering in 2002. His professional activity is currently balanced between researching at the University of Modena and Reggio Emilia, and consulting as a system engineer and network architect. His research interests focus on congestion control and multimedia services in next generation Internet. Michele Borri has been participating to national research projects promoted by the Italian National Research Council (CNR). Maurizio Casoni is Associate Professor in Telecommunications at the University of Modena and Reggio Emilia. He graduated with honors in Electrical Engineering at the University of Bologna in 1991, with a grant by Telecom Italia and received the Ph.D. degree also in Electrical Engineering from the University of Bologna, in 1995. In 1995 he was with the Computer Science Department at Washington University in St. Louis, MO, as a research fellow where he worked on ATM broadband switching architectures. He has studied ATM broadband switching architectures and Clos architectures for the design of large photonic switches in the framework of the European Projects ATMOS and KEOPS. He has also investigated the performance of 3rd generation UMTS systems. His current research interests deal with Optical Networking, mainly focusing on Optical Burst Switching, and Satellite Networks. He currently holds the course of Interconnection Systems for undergraduate students and the course of Switching Systems for graduate students of Telecommunications Engineering. Maria Luisa Merani is currently an associate professor of Telecommunication Networks at the University of Modena and Reggio Emilia, Department of Information Engineering. She is an IEEE Senior member and has served on the Technical Program Committees of several major communication conferences (IEEE ICC, IEEE Globecom, IEEE VTC, APCC). In 2005 she has been technical program cochair of the second IEEE International Symposium in Wireless Communication Systems. In 2007 she will be the Wireless Symposium chair of IEEE Globecom. At present she is involved in research on congestion control for next generation Internet and on multicast video streaming. Her most recent research interests are related to the area of radio communications, with emphasis on performance evaluation of mobile radio systems, 3G data networking and transport solutions for optical networks. Maria Luisa Merani received both her M.Sc. (summa cum laude) and Ph.D. in electrical engineering from the University of Bologna, Italy, in the academic years 1985/86 and 1991/92, respectively. In 1992 she spent one year at the Computer Science Department of the University of California in Los Angeles, CA, USA.     

A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and bluetooth Co-existence applications

This paper describes a high-performance WLAN 802.11a/b/g radio transceiver, optimized for low-power in mobile applications, and for co-existence with cellular and Bluetooth systems in the same terminal. The direct-conversion transceiver architecture is optimized in each mode for low-power operation without compromising the challenging RF performance targets. A key transceiver requirement is a sensitivity of -77 dBm (at the LNA input) in 54 Mb/s OFDM mode while in the presence of a GSM1900 transmitter interferer. The receiver chain achieves an overall noise figure of 2.8/3.2 dB, consuming 168/185 mW at 2.8 V for the 2.4/5GHz bands, respectively. Signal loopback and transmit power detection techniques are used in conjunction with the baseband modem processor to calibrate the transmitter LO leakage and the transceiver I/Q imbalances. Fabricated in a 70 GHz f/sub T/ 0.25-/spl mu/m SiGe BiCMOS technology for system-in-package (SiP) use, the dual-band, tri-mode transceiver occupies only 4.6 mm/sup 2/.     

A 8.75-11.2-GHz,low phase noise fractional-N synthesizer for 802.11a/b/g zero-IF transceiver

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented.The mathematical models for the behavior of the synthesizer’s spur and phase noise are analyzed,and the optimization methodology is proposed.Measurement results exhibits that the frequency synthesizer’s integrated phase noise is less than 1°(1 kHz to 100 MHz)with a 4.375 GHz carrier(after divide-by-2),and the reference frequency spur is below-60 dBc operating with a 33 MHz reference clock.The frequency synthesizer is fabricated on a standard 0.13μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.     

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.     

A 2.4-GHz 0.25-/spl mu/m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

A dual-mode transceiver integrates the transmitter of 0-dBm output power and the receiver for both Bluetooth with -87 dBm sensitivity and 802.11b with -86 dBm sensitivity in a single chip. A direct-conversion architecture enables the maximum reuse and the optimal current consumption of the various building blocks in each mode for a low-cost and low-power solution. A single-ended power-amplifer (PA) driver transmits the nominal output power of 0 dBm with 18-dB gain control in 3-dB steps. Only little area overhead is required in the baseband active filter and programmable gain amplifier (PGA) to provide the dual-mode capability with optimized current consumption. The DC-offset cancellation scheme coupled with PGAs implements the very low high-pass cutoff frequency with a smaller area than required by a simple coupling capacitor. Fabricated in 0.25-/spl mu/m CMOS process, the die area is 8.4 mm/sup 2/ including pads, and current consumption in RX is 50 mA for Bluetooth and 65 mA for 802.11b from a 2.7-V supply.     

A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard

A fully integrated CMOS direct-conversion 5-GHz transceiver with automatic frequency control is implemented in a 0.18-/spl mu/m digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution The transceiver consumes 150 mW in receive mode and 380 mW in transmit mode while transmitting +15-dBm output power. The receiver achieves a sensitivity of better than -93.7dBm and -73.9dBm for 6 Mb/s and 54 Mb/s, respectively (even using hard-decision decoding). The transceiver achieves a 4-dB receive noise figure and a +23-dBm transmitter saturated output power. The transmitter also achieves a transmit error vector magnitude of -33 dB. The IC occupies a total die area of 11.7 mm/sup 2/ and is packaged in a 48-pin LPCC package. The chip passes better than /spl plusmn/2.5-kV ESD performance. Various integrated self-contained or system-level calibration capabilities allow for high performance and high yield.     

Designing a fair scheduling mechanism for IEEE 802.11 wireless LANs

A fair scheduling mechanism called distributed elastic round robin (DERR) is proposed in this letter for IEEE 802.11 wireless LANs operated in a distributed manner. To quantify the fairness, we not only derive its fairness bound, but also observe the fairness through ratios of throughput and weight using a simulation approach. By numerical comparisons among DERR, distributed deficit round robin (DDRR), and IEEE 802.11e, we demonstrate that DERR outperforms the other two mechanisms in performance and fairness.