固化残余应力对倒装焊器件热-机械可靠性的影响

采用底充胶的与固化过程相关的粘弹性力学模型,通过有限元仿真的方法,模拟了底充胶的整个固化过程,计算出了热循环加载下硅片、底充胶/硅片界面、底充胶内部的应力分布及其幅值大小。结果表明:底充胶的固化过程及由此产生的固化残余应力不但使得硅片中的最大垂直开裂应力位置偏离中心线达1.6 mm之多,而且还劣化了热循环加载下底充胶中应力幅值约6.25%。最后得出了固化残余应力对倒装焊器件热–机械可靠性的影响是不可忽略的结论。     

固化残余应力对倒装焊底充胶可靠性的影响

通过对考虑固化过程影响的倒装焊底充胶的热－机械有限元模拟，分析了底充胶在固化过程中因体积收缩，材料的刚度增加及受周围材料的约束所产生的固化残余应力对随后热循环加载下底充胶应力分布与幅值的影响，得出了固化过程及其固化残余应力不但进一步劣化了热循环加载下底充胶中的应力值，而且还影响了随后底充胶的热－机械疲劳可靠性的结论。     

底充胶固化工艺对低k倒装焊器件可靠性的影响

利用四点弯曲实验测试了一组芯片(30片)的强度,使用威布尔统计模型描述了芯片失效率的分布,预测了在后续热循环过程中芯片的失效概率。通过有限元软件研究了底充胶固化工艺对芯片上方垂直开裂应力、焊点等效塑性应变及低k层最大等效应力的影响。结果表明:与未经固化的相比,底充胶固化工艺使得芯片的失效率从0.08%增大到0.37%,焊点的等效塑性应变增大约7倍,低k层的最大等效应力增大约18%。     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

湿热环境下倒装焊无铅焊点的可靠性

对板上倒装芯片底充胶进行吸湿实验,并结合有限元分析软件研究了底充胶在湿敏感元件实验标准MSL—1条件下吸湿和热循环阶段的解吸附过程,测定了湿热环境对Sn3.8Ag0.7Cu焊料焊点可靠性的影响,并用蠕变变形预测了无铅焊点的疲劳寿命。结果表明:在湿热环境下,底充胶材料内部残留的湿气提高了焊点的应力水平。当分别采用累积蠕变应变和累积蠕变应变能量密度寿命预测模型时,无铅焊点的寿命只有1740和1866次循环周期。     

倒装焊封装中无铅焊点在封装工艺中的热机械力学分析

采用粘塑性Garofalo—Arrhenius模型描述无铅焊料的蠕变行为，确定了96．5Sn3.5Ag焊点材料的模型参数。采用与固化过程相关的粘弹性力学模型描述倒装焊底充胶的力学行为。利用有限元法模拟了无铅板上倒装焊在封装工艺及热循环条件下的应力应变行为。结果表明由于无铅技术在封装中的引入，封装工艺对倒装焊器件的影响更为重要。     

板上芯片固化后残余应力分布的有限元模拟

用有限元模拟研究了板上芯片固化后残余应力的分布.在FR4及陶瓷分别作基板的两种情况下,残余应力分布最显著的差异是等效应力分布不同.讨论了基板厚度及粘合胶厚度对残余应力的影响,表明采用陶瓷基板时增加粘合胶的厚度以降低残余应力来作为低应力封装的一种手段是可行的.硅压阻传感芯片测量结果与计算机模拟结果的比较表明,计算机模拟值与实验测量值比较接近,测量值的正负区间与模拟值的正负区间吻合     

板上芯片固化后残余应力分布的有限元模拟

用有限元模拟研究了板上芯片固化后残余应力的分布.在FR4及陶瓷分别作基板的两种情况下,残余应力分布最显著的差异是等效应力分布不同.讨论了基板厚度及粘合胶厚度对残余应力的影响,表明采用陶瓷基板时增加粘合胶的厚度以降低残余应力来作为低应力封装的一种手段是可行的.硅压阻传感芯片测量结果与计算机模拟结果的比较表明,计算机模拟值与实验测量值比较接近,测量值的正负区间与模拟值的正负区间吻合.     

FCOB器件在热循环载荷下的界面层裂研究

界面层裂是塑封半导体器件的主要失效模式之一。采用通用有限元软件MSC.MARC,研究了FCOB(基板倒装焊)器件在热循环(–55~+125℃)载荷作用下,底充胶与芯片界面的层裂问题。结果表明:底充胶与芯片界面最易出现分层,分层扩展的位置都在该界面的边缘拐角处;如果分层导致底充胶开裂,开裂的方向大约是35°。     

Die stress characterization in flip chip on laminate assemblies

Minimizing device side die stresses is especially important when multiple copper/low-k interconnect redistribution layers are present. Mechanical stress distributions in packaged silicon die resulting during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150/spl deg/C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.     

In process stress analysis of flip-chip assemblies during underfill cure

Low cost flip chip on board assemblies are analyzed during the underfill cure process to determine residual stress generation. In situ stress measurements are performed over the active face of the die during processing and relative in-plane stresses are measured. Experimental measurements are made using flip-chip test vehicles, based on the Sandia National Laboratories’ ATC04 assembly test chip. Four different commercial underfill materials have been evaluated and a relative comparison is presented with respect to the residual stresses produced by each underfill on the flip-chip assemblies. Significant stress variations are observed between the four underfills studied. Correlation between the glass transition temperature (T_g) and storage modulus (G^′) are made relative to residual stresses produced during underfill cure. Stress relaxation characteristics are also evaluated for the low cost flip-chip assemblies.     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

Package design and materials selection optimization for overmolded flip chip packaging

In overmolded flip chip (OM-FC) packaging, interface delamination-particularly at the die/underfill interface-is often expected to be a main type of failure mode. In this paper, a systematic stress analysis is performed by means of numerical simulations for the optimal design of package geometries and materials combinations. The behavior of the interfacial stresses at the die/underfill and die/mold-compound (MC) during the molding process is investigated, followed by a parametric study to examine the effects of the package geometries and materials parameters including the underfill fillet size, die thickness, die size, die standoff height, solder mask design pattern, MC used as underfill material, MC properties, etc., on the interfacial stresses. The results demonstrate that a proper selection of these parameters can mitigate the interfacial stresses, and thus is important for the reliability of the low-cost OM-FC packages.     

Evaluation of Strain Measurement in a Die-to-Interposer Chip Using In Situ Synchrotron X-Ray Diffraction and Finite-Element Analysis

To decrease the size of portable devices, this study incorporates a stacked three-dimensional integrated circuit architecture into advanced packaging techniques. The traditional FR-4 substrate was substituted with silicon interposers. Because silicon is rigid and highly resistant to deformation, this minimizes thermal stress caused by thermal expansion mismatch in the structure. This study shows that underfill applied stress to the dies when the temperature was varied, threatening the devices. Damage was most likely to occur at the die corners. The stresses were measured in situ at different temperatures using synchrotron radiation x-ray analysis. Simulation results confirm the measured data trends.     

Reliability assessment and hygroswelling modeling of FCBGA with no-flow underfill

In the flip-chip ball grid array (FCBGA) assembly process, no-flow underfill has the advantage over traditional capillary-flow underfill on shorter cycle time. Reliability tests are performed on both unmolded and molded FCBGA with three different types of no-flow underfill materials. The JEDEC Level-3 (JL3) moisture preconditioning, followed by reflow and pressure cooker test (PCT) is found to be a critical test for failures of underbump metallization (UBM) opening and underfill/die delamination. In this paper, various types of modeling techniques are applied to analyze the FCBGA-8×8 mm on moisture distribution, hygroswelling behavior, and thermomechanical stress. For moisture diffusion modeling, thermal-moisture analogy is used to calculate the degree of moisture saturation in the multi-material system of FCBGA. The local moisture concentration along the critical interface, e.g. die/underfill, is critical for delamination, because the moisture weakens the interfacial adhesion strength, generates internal vapor pressure during reflow, and induces tensile hygroswelling stress on UBM during PCT. The results of moisture distribution can be used as loading input for the subsequent hygroswelling modeling. The magnitude of hygroswelling stress acting on UBM is found to be greater than the thermal stress induced during reflow, both in tensile mode which may cause the UBM-opening failure. Underfill with lower saturated moisture concentration (C_sat) and coefficient of moisture expansion (CME) are found to induce lower UBM stress and has better reliability results. Molded package generally has higher stress level than unmolded package. Parametric studies are performed to study the effects of no-flow underfill materials, package type (molded vs. unmolded), die thickness, and substrate size on the stresses of UBM during reflow and PCT.     

Vertical die crack stresses of Flip Chip induced in major package assembly processes

This paper focuses on the FEM prediction of vertical die crack stresses in a Flip Chip configuration, induced in the major package assembly processes and subsequent thermo-mechanical loading. An extended Maxwell model is used to describe the time dependent inelastic behavior of the solder bumps. Two types of viscoelastic models, describing the mechanical properties of underfill resin during and after the curing process, are used. The die stresses caused by both the soldering and the underfill curing processes are obtained. These stresses are used as initial stress-state for the further modeling of subsequent thermal cycling. Using this methodology, the complete die stress evolution in a selected Flip Chip can be obtained, the physics of thermal stress induced vertical die cracks can be better understood and the possible die cracks can be reliably predicted.     

Thermomechanical reliability of underfilled BGA packages

The effect of underfill on various thermomechanical reliability issues in super ball grid array (SBGA) packages is studied in this paper. Nonlinear finite element models with underfill and no underfill are developed taking into consideration the process-induced residual stresses. In this study, the solder is modeled as time and temperature-dependent, while other materials are modeled temperature and direction-dependent, as appropriate. The stress/strain variations in the package due to thermal cycling are analyzed. The effect of underfill is studied with respect to magnitude and location of time-independent plastic strain, time-dependent creep strain and total inelastic strain in solder balls. The effect of copper core on the solder ball strains is presented. The possibility of delamination at the interposer-underfill interface as well as substrate-underfill interface is studied with the help of qualitative interfacial stress analysis. Results on SBGA packages indicate that the underfill does not always enhance BGA reliability, and that the properties of the underfill have a significant role in the overall reliability of the BGA packages. The predicted number of thermal cycles to solder joint fatigue are compared with the existing experimental data on similar nonunderfilled BGA packages.     

Measurement of underfill interfacial and bulk fracture toughness in flip-chip packages

Flip-chip package reliability is greatly improved by encapsulating the solder interconnections between a polymeric encapsulant or underfill. However, thermo-mechanical stresses within such packages often lead to failures initiating in the vicinity of chip and underfill interface. In this study, we present experimental results geared towards measuring and understanding such failure mechanisms. We provide the bulk fracture toughness of the underfill material and interfacial fracture toughness between the underfill material and the silicon die. The bulk and interfacial fracture toughness measurements are performed as a function of temperature. We use the single edge notch bending test to calculate the bulk fracture toughness of the underfill and to measure the interfacial fracture toughness, we use a novel technique referred to as the wedge delamination method. The wedge delamination method provides substantial advantage in measuring the interfacial fracture toughness for brittle materials over traditional methods. Using the wedge delamination method we compare the fracture strength between the underfill and silicon at the front-face and side-wall interfaces. Additionally, the influence of dicing technique on fracture toughness is also investigated.