真实缺陷的矩形模型及其关键面积计算

在集成电路(IC)中,为了进行有效的成品率估计和故障分析,与光刻有关的缺陷形状通常假设为圆模型.然而,真实缺陷的形状多种多样.本文提出一种真实缺陷的矩形模型及与之相关的关键面积计算模型,该模型既考虑了真实缺陷的形状又考虑了IC版图布线的特点.在缺陷引起故障概率预测方面,仿真结果表明新模型比圆模型更接近真实缺陷引起的故障概率.     

A Novel Algorithm to Extract Weighted Critical Area

导体故障分析是一种列举与缺陷有关的集成电路版图中可能出现桥连的技术,计算带权关键面积是限制其性能的主要因素.文中提出了一种基于数学形态学和真实缺陷矩形模型提取带权关键面积的新算法,该算法不需要将版图上的线网拆分为矩形,也不需要合并矩形对的带权关键面积.实验结果验证了新算法的有效性.     

提取带权关键面积的新算法

导体故障分析是一种列举与缺陷有关的集成电路版图中可能出现桥连的技术,计算带权关键面积是限制其性能的主要因素.文中提出了一种基于数学形态学和真实缺陷矩形模型提取带权关键面积的新算法,该算法不需要将版图上的线网拆分为矩形,也不需要合并矩形对的带权关键面积.实验结果验证了新算法的有效性.     

一种快速计算和优化关键面积提高成品率的方法

成品率驱动设计(DFY)已经成为集成电路设计的必然趋势。基于随机缺陷的DFY设计的主要目标是通过优化版图的关键面积来提高成品率。针对版图局部修改后关键面积的重新计算问题,提出了一种快速计算关键面积的方法,不仅能快速比较各种修改方案的优劣,还能利用计算速度的优势,快速得到最优的设计修改方案,极大的降低了DFY设计的计算时间成本,提高集成电路产品的成品率。     

基于线性规划的关键面积最小化方法

随着集成电路(IC)技术的不断发展,尤其在90nm和65 nm技术节点,集成电路制造业的投资剧增而随机成品率却在下降.为了提升随机成品率,需要在布线或后布线阶段减小关键面积.文中提出一种基于线性规划降低关键面积的方法,使关键面积在一组条件约束下,通过版图中一些特征量的变化,建立起一个线性规划模型,然后求其最优解,进而得出关键面积的最小值.该方法的优点是把一个版图优化问题转化为数学问题,使问题更精确化,从而为成品率的优化提供了一条新途径.     

基于刻蚀工艺的IC关键面积计算模型与实现方法

在 IC的制造过程中 ,由于工艺的随机扰动 ,过刻蚀和欠刻蚀造成了导线条的宽度和线间距的变化 .论文在分析过刻蚀和欠刻蚀对 IC版图影响的基础上 ,提出了基于工艺偏差影响的 IC关键面积计算新模型和实现方法 .模拟实验表明模拟结果与理论分析是一致的     

基于刻蚀工艺的IC关键面积计算模型与实现方法

在IC的制造过程中,由于工艺的随机扰动,过刻蚀和欠刻蚀造成了导线条的宽度和线间距的变化.论文在分析过刻蚀和欠刻蚀对IC版图影响的基础上,提出了基于工艺偏差影响的IC关键面积计算新模型和实现方法.模拟实验表明模拟结果与理论分析是一致的.     

基于刻蚀工艺的IC关键面积计算模型与实现方法

在IC的制造过程中,由于工艺的随机扰动,过刻蚀和欠刻蚀造成了导线条的宽度和线间距的变化.论文在分析过刻蚀和欠刻蚀对IC版图影响的基础上,提出了基于工艺偏差影响的IC关键面积计算新模型和实现方法.模拟实验表明模拟结果与理论分析是一致的.     

用于微波功率器件的层级式片上功率合成技术

提出了一个包含版图分布参数和引线寄生参数在内的微波功率HBT的宏模型,建立了通过微波仿真进行器件结构优化的技术方法.基于以上模型和方法,较为全面地评估了实际器件中各寄生参数对器件输出功率的影响,继而提出了片上功率合成的层级式技术方案.数值计算指出,采用该方案,在相同版图面积并且器件的线性度等关键性指标得到保证的情况下,可有效地提高SiGe HBT的功率容量.     

一种改进的考虑划痕的关键面积计算模型和方法

关键面积计算对于集成电路成品率的准确预测有着重要的意义。为了得到精确的结果,关键面积计算需要根据缺陷形状的不同选择适当的缺陷模型。针对化学机械研磨引入的划痕,提出了一种线性缺陷模型来计算其关键面积。在此基础上进一步考虑了线端效应的影响,对考虑划痕的关键面积计算模型提出了改进。实验结果表明改进后模型的计算结果更为准确。     

Chip area estimation method for VLSI chip floor plan

A chip area estimation method is presented, which consists of intrablock area calculation based on empirically obtained block data and interblock channel area calculation. The method is used in a chip floor program for hierarchical standard-cell VLSI layout design. By applying to several practical circuits, it is shown that the estimation error is within ±10%.     

Accurate estimation of defect-related yield loss in reconfigurableVLSI circuits

A general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits is presented. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensitivity to manufacturing defects of varying sizes. The important concept addressed is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cell's critical area (CA) for accurate yield estimation. Two examples-a 256 kb SRAM and reconfigurable 32×32 port 32 b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method     

CMOS layout design of the hysteresis McCulloch-Pitts neuron

A McCulloch-Pitts neuron is the simplified neuron model which has been successfully used for many optimisation problems. The neural network with the hysteresis property can suppress the oscillatory behaviours of neural dynamics so that the convergence time is shortened. In this paper, digital CMOS layout design of the hysteresis McCulloch-Pitts neuron is presented. Based on simulation results using the hysteresis McCulloch-Pitts binary neuron model, a 6-bit fixed point 2's complement arithmetic was adopted for the calculation of the input U of each neuron. Each neuron needs 204 transistors and requires a 399 lambda *368 lambda layout area using the MOSIS scalable CMOS/bulk (SCMOS) VLSI technology with 2 mu m rule of P well, double level metal. Layout design of the hysteresis McCulloch-Pitts neuron chip was completed, and fabrication of the chip and the design for the test circuit for the fabricated CMOS VLSI chip are underway at present.<>     

Computer-aided design for integrated circuits: trying to bridge the gap

CAD performance in the field of simulation, testing, and layout is compared to the increase of digital integrated systems complexity. This complexity already exceeds the fundamental limits of existing software, especially in the testing area. On the other hand, fully manual layout of VLSI leads to unreasonably long design times and extremely high risks. This will favor design automation methods in layout. Testability and layout will most likely impose some sacrifice of VLSI overcapacity to a more structured system architecture. This architecture will lead to testable dedicated VLSI system design through the use of automated design software to keep development costs low.     

Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization

This paper proposes a yield optimization method for standard cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield enhanced standard cells and the proposed method automatically creates yield enhanced cell layouts by decompacting the original cell layout using linear programming. We develop a novel accurate linear delay model which approximates the difference from the original delay and use this model to formulate the timing constraints into linear programming. Experimental results show that the proposed method can pick up the yield variants of a cell layout from the tradeoff curve of cell delay versus critical area and is used to create the yield enhanced cell library which is essential to realize yield-aware VLSI design flows.     

VLSI版图参数提取的分布式并行算法

在用边界元法提取版图参数时,经常会遇到非均匀介质的情况。对这类问题若直接用传统的边界元分区方法求解,处理起来比较麻烦,尤其当非均匀性较严重时,边界元法计算简单方便、速度快的优点会大大削弱。针对这一现象。本文提出了边界元分区问题的分布式并行算法。将它用于一个由天台工作站组成的分布式环境中对ＶＬＳＩ版图参数进行提取,运行时间比传统方法明显减少,证明该算法加快了求解的速度,具有并行、高效的特点,取得了良     

VLSI layout of binary tree structures

Algorithms are presented in this paper for VLSI layout of come binary tree structures. In particular, we consider X-Tree and Hypertree multicomputers and show that they can be laid out in O(8n) and O(n√n) area respectively. Our algorithms are based on an original algorithm proposed by Horowitz and Zorat for an arbitrary tree structure. The layout follows Thompson's VLSI model of computation that allows two layers of metalization.     

An interactive VLSI CAD tool for yield estimation

The yield of a VLSI chip depends on the sensitivity of the chip to defects occurring during the fabrication process, among other factors. To predict this sensitivity, one usually needs to compute the so-called critical area (A_c), which reflects how many and how large the defects must be in order to result in a circuit failure. The main computational problem in yield estimation is to calculate A_c efficiently for complicated, irregular layouts. A novel approach is suggested for this problem that results in an algorithm that will solve it efficiently. This paper provides an interactive, accurate, and fast method for the evaluation of critical area as a design tool; the tool utilizes good visual feedback to allow layout improvement for higher yield. The algorithm is compared to other yield-prediction methods, which use either the Monte Carlo approach (VLASIC) or a deterministic approach (SCA); the algorithm is shown to be faster. It also has the advantage that it can graphically show a detailed `defect sensitivity map' that can assist a chip designer in improving the yield of his/her layout     

时延驱动的VLSI版图规划算法

本文提出了时延驱动布图规划的思想。在用改进的广义力矢量法优化功能单元间连线时延的同时，运算非线性规划的方法进一步优化关键路径上功能单元的时延及连线时延。结果表明，这是一种有效的优化版图时延的方法。     

Timing driven floorplanning for general cells

The idea of timing driven floorplanning is presented. While optimising the interconnection (wire) delay between cells using the weighted min-cut method, the authors used the nonlinear programming method to reduce both the cell and interconnection delays in the critical paths. Experiments on the examples produced promising results, indicating that the method is effective at optimising the layout phase in VLSI design