共查询到20条相似文献,搜索用时 46 毫秒
1.
Jin-Ki Kim Sakui K. Sung-Soo Lee Itoh Y. Suk-Chon Kwon Kanazawa K. Ki-Jun Lee Nakamura H. Kang-Young Kim Himeno T. Jang-Rae Kim Kanda K. Tae-Sung Jung Oshima Y. Kang-Deog Suh Hashimoto K. Sung-Tae Ahn Miyamoto J. 《Solid-State Circuits, IEEE Journal of》1997,32(5):670-680
Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm2 and an effective cell size of 1.1 μm2 相似文献
2.
Tae-Sung Jung Young-Joon Choi Kang-Deog Suh Byung-Hoon Suh Jin-Ki Kim Young-Ho Lim Yong-Nam Koh Jong-Wook Park Ki-Jong Lee Jung-Hoon Park Kee-Tae Park Jhang-Rae Kim Jeong-Hyong Yi Hyung-Kyu Lim 《Solid-State Circuits, IEEE Journal of》1996,31(11):1575-1583
For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-μm CMOS technology, resulting in a 117 mm2 die size and a 1.1 μm2 effective cell size 相似文献
3.
Imamiya K. Sugiura Y. Nakamura H. Himeno T. Takeuchi K. Ikehashi T. Kanda K. Hosono K. Shirota R. Aritome S. Shimizu K. Hatakeyama K. Sakui K. 《Solid-State Circuits, IEEE Journal of》1999,34(11):1536-1543
A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm2, which realizes a 130-mm2 , 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput 相似文献
4.
Ohkawa M. Sugawara H. Sudo N. Tsukiji M. Nakagawa K. Kawata M. Oyama K.-i. Takeshima T. Ohya S. 《Solid-State Circuits, IEEE Journal of》1996,31(11):1584-1589
In order to realize high-capacity and low-cost flash memory, we have developed a 64-Mb flash memory with multilevel cell operation scheme. The 64-Mb flash memory has been achieved in a 98 mm2 die size by using four-level per cell operation scheme, NOR type cell array, and 0.4-μm CMOS technology. Using an FN type program/erase cell allows a single 3.3 V supply voltage. In order to establish fast programming operation using Fowler-Nordheim (FN)-NOR type memory cell, we have developed a highly parallel multilevel programming technology. The drain voltage controlled multilevel programming (DCMP) scheme, the parallel multilevel verify (PMV) circuit, and the compact multilevel sense-amplifier (CMS) have been implemented to achieve 128 b parallel programming and 6.3 μs/Byte programming speed 相似文献
5.
Ohnakado T. Onoda H. Sakamoto O. Hayashi K. Nishioka N. Takada H. Sugahara K. Ajika N. Satoh S. 《Electron Devices, IEEE Transactions on》1999,46(9):1866-1871
The P-channel DINOR flash memory, which uses the band-to-band tunneling induced hot electron (BBHE) program method having the advantages of high scalability, high efficiency, and high oxide reliability, was fabricated by 0.35-μm-rule CMOS process and was investigated in detail. An ultra-high programming throughput of less than 8 ns/byte (=4 μs/512 byte) and a low current consumption of less than 250 μA were achieved by utilizing 512-byte parallel programming. Furthermore, we investigated its endurance characteristics up to 106 program/erase cycles, and window narrowing and Gm degradation were found to be very small even after 106 cycles. It is thought that the BBHE injection point contributes to the G m stability and the oxide-damage-reduced operation contributes to the good window narrowing characteristics. The P-channel DINOR flash memory realizing high programming throughput with low power consumption is one of the strongest candidates for the next generation of high-performance, low-voltage flash memories 相似文献
6.
To realize a low-cost and high-speed programming NAND flash memory, a new programming scheme, a “dual-page programming scheme,” has been proposed. This architecture drastically increases the program throughput without circuit area overhead. In the proposed scheme, two memory cells are programmed at the same time using only one page buffer. Therefore, the page size, i.e., the number of memory cells programmed simultaneously, is doubled and the program speed is improved. As the number of page buffers required in the proposed scheme is the same as that in the conventional one, there is no circuit area increase. This novel operation is made possible by using a bitline as a dynamic latch to temporarily store the program data. As a result, the programming is accelerated by 73% in a 1-Gb generation and 62% in a 4-Gb generation, 18.2-MB/s 1-Gb or 30.7-MB/s 4-Gb NAND flash memory can be realized with this new architecture 相似文献
7.
Fiocchi C. Torelli G. Ghezzi S. Maccarrone M. 《Solid-State Circuits, IEEE Journal of》1997,32(1):100-104
This paper describes a program load voltage generator for flash memories. It is based on an adaptive feedback loop which senses the current delivered to the memory cells during programming and adjusts the output voltage accordingly to compensate for the voltage drop caused by the programming current across the bit-line select transistors. The proposed circuit (silicon area=0.065 mm2) was integrated in a 0.8-μm CMOS 4 Mb flash memory device (0.6 μm in the matrix). Experimental evaluations showed that very effective compensation is achieved, with bit-line voltage kept at the desired value during the whole programming operation. A spread as small as 70 mV was measured between the single-bit and 16-b programming cases 相似文献
8.
Kang-Deog Suh Byung-Hoon Suh Young-Ho Lim Jin-Ki Kim Young-Joon Choi Yong-Nam Koh Sung-Soo Lee Suk-Chon Kwon Byung-Soon Choi Jin-Sun Yum Jung-Hyuk Choi Jang-Rae Kim Hyung-Kyu Lim 《Solid-State Circuits, IEEE Journal of》1995,30(11):1149-1156
While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm2 die size, improved yields, and a simple process with 0.5 μm CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA 相似文献
9.
Tanaka T. Tanaka Y. Nakamura H. Sakui K. Oodaira H. Shirota R. Ohuchi K. Masuoka F. Hara H. 《Solid-State Circuits, IEEE Journal of》1994,29(11):1366-1373
This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure. A 3 V-only experimental NAND flash memory, developed in a 0.7-μm NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-μs random access time with a 2.7-V power supply. The page-programming is completed after the 40-μs program and 2.8-μs verify read cycle is iterated 4 times. The block-erasing time is 10 ms 相似文献
10.
Takeuchi K. Kameda Y. Fujimura S. Otake H. Hosono K. Shiga H. Watanabe Y. Futatsuyama T. Shindo Y. Kojima M. Iwai M. Shirakawa M. Ichige M. Hatakeyama K. Tanaka S. Kamei T. Fu J.-Y. Cernea A. Li Y. Higashitani M. Hemink G. Sato S. Oowada K. Lee S.-C. Hayashida N. Wan J. Lutze J. Tsao S. Mofidi M. Sakurai K. Tokiwa N. Waki H. Nozawa Y. Kanazawa K. Ohshima S. 《Solid-State Circuits, IEEE Journal of》2007,42(1):219-232
A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm2, has been successfully developed. This is the world's first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including the select transistors is 0.0075 mum2 per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically improved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4kB to 8kB. In addition, noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size 相似文献
11.
《Solid-State Circuits, IEEE Journal of》2009,44(4):1227-1234
12.
Tae-Sung Jung Do-Chan Choi Sung-Hee Cho Myong-Jae Kim Seung-Keun Lee Byung-Soon Choi Jin-Sun Yum San-Hong Kim Dong-Gi Lee Jong-Chang Son Myung-Sik Yong Heung-Kwun Oh Sung-Bu Jun Woung-Moo Lee Haq E. Kang-Deog Suh Ali S.B. Hyung-Kyu Lim 《Solid-State Circuits, IEEE Journal of》1997,32(11):1748-1757
A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-μm triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm2, and the effective cell size including the overhead of string select transistors is 2.0 μm2 相似文献
13.
《Solid-State Circuits, IEEE Journal of》2009,44(1):208-216
A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is fabricated by 45 nm floating-gate CMOS and single-crystal Si layer stacking technologies. To support fully compatible device performance and characteristics with conventional planar device, shared bitline architecture including Si layer-dedicated decoder and Si layer-compensated control schemes are also developed. By using the architecture and the design techniques, a memory cell size of 0.0021 mum2/bit per unit feature area which is smallest cell size and 2.5 MB/s program throughput with 2 kB page size which is almost equivalent performance compared to conventional planar device are realized. 相似文献
14.
Kobayashi S. Nakai H. Kunori Y. Nakayama T. Miyawaki Y. Terada Y. Onoda H. Ajika N. Hatanaka M. Miyoshi H. Yoshihara T. 《Solid-State Circuits, IEEE Journal of》1994,29(4):454-460
A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm2 and the chip measures 5.8×5.0 mm 2. The divided bit line structure realizes a small NOR type memory cell 相似文献
15.
Campardo G. Micheloni R. Commodaro S. Yero E. Zammattio M. Mognoni S. Sacco A. Picca M. Manstretta A. Scotti M. Motta I. Golla C. Pierin A. Bez R. Grossi A. Modelli A. Visconti A. Khouri O. Torelli G. 《Solid-State Circuits, IEEE Journal of》2000,35(11):1655-1667
This paper presents a 3-V-only 64-Mb 4-level-cell (2-b/cell) NOR-type channel-hot-electron (CHE) programmed flash memory fabricated in 0.18-μm shallow-trench isolation CMOS technology. The device (die size 40 mm2) is organized in 64 1-Mb sectors. Hierarchical column and row decoding ensures complete isolation between different sectors during any operation, thereby increasing device reliability while still providing layout area optimization. Staircase gate-voltage programming is used to achieve narrow threshold-voltage distributions. The same program throughput as for bilevel CHE-programmed memories is obtained, thanks to parallel programming. A mixed balanced/unbalanced sensing approach allows efficient use of the available threshold window. Asynchronous (130-ns access time) and burst-mode (up to 50-MHz data rate) reading is possible. Both column and row redundancy is provided to ensure extended failure coverage. Error correction code techniques, correcting 1 failed over 32 data cells, are also integrated 相似文献
16.
June Lee Heung-Soo Im Dae-Seok Byeon Kyeong-Han Lee Dong-Hyuk Chae Kyong-Hwa Lee Sang Won Hwang Sung-Soo Lee Young-Ho Lim Jae-Duk Lee Jung-Dal Choi Young-Il Seo Jong-Sik Lee Kang-Deog Suh 《Solid-State Circuits, IEEE Journal of》2002,37(11):1502-1509
A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained. 相似文献
17.
To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme 相似文献
18.
Nozoe A. Kotani H. Tsujikawa T. Yoshida K. Furusawa K. Kato M. Nishimoto T. Kume H. Kurata H. Miyamoto N. Kubono S. Kanamitsu M. Koda K. Nakayama T. Kouro Y. Hosogane A. Ajika N. Koyashi K. 《Solid-State Circuits, IEEE Journal of》1999,34(11):1544-1550
A 256-Mb flash memory is fabricated with a 0.25-μm AND-type memory cell and 2-bit/cell multilevel technique on a 138.6-mm2 die. Parallel decoding of four memory threshold voltage levels to 2-bit logical values prevents throughput degradation due to multilevel operation. This parallel decoding has been achieved by sense latches and data latches connected to each bitline. Tight distribution of memory cell threshold voltage is essential to reliable multilevel operation. This chip has several measures to deal with the factors that widen the memory cell Vth. The effect of adjacent memory cell's Vth is eliminated by using an AND-type flash memory cell. An initial distribution width of 0.1 V is achieved. The wordline voltage, which has negative temperature dependency, compensates the positive dependency of memory cell Vth. In the -5-75°C range, memory threshold Vth deviation is reduced from the conventional 0.19-0.07 V. Conventionally, the number of programs without erase operation per one sector is limited by the limitations from program disturb. This chip introduced a new rewrite scheme, and this limit is increased from the conventional 10-2048+64 times/sector 相似文献
19.
A 70 nm 16 Gb 16-Level-Cell NAND flash Memory 总被引:1,自引:0,他引:1
Shibata N. Maejima H. Isobe K. Iwasa K. Nakagawa M. Fujiu M. Shimizu T. Honma M. Hoshi S. Kawaai T. Kanebako K. Yoshikawa S. Tabata H. Inoue A. Takahashi T. Shano T. Komatsu Y. Nagaba K. Kosakai M. Motohashi N. Kanazawa K. Imamiya K. Nakai H. Lasser M. Murin M. Meir A. Eyal A. Shlick M. 《Solid-State Circuits, IEEE Journal of》2008,43(4):929-937
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more. 相似文献
20.
Umezawa A. Atsumi S. Kuriyama M. Banba H. Imamiya K. Naruke K. Yamada S. Obi E. Oshikiri M. Suzuki T. Tanaka S. 《Solid-State Circuits, IEEE Journal of》1992,27(11):1540-1546
An experimental 4-Mb flash EEPROM has been developed based on 0.6-μm triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0×1.8 μm2 has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11×6.95 mm2, and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm2 by using the minimal cell size (2.0×10 μm2) 相似文献