有限元方法求解化学气相淀积反应器模型(Ⅱ)——热壁反应器模型及反应器中流动及传递过程的分析

分析了热壁化学气相淀积反应器在流型、温度和浓度分布以及淀积速率等方面与冷壁反应器的异同,探讨了流动特性、传递过程和反应器几何尺寸对淀积过程的影响,为淀积不同薄膜时反应器的选型及设计提供了方法和依据.     

化学气相淀积反应器中成核与成膜控制

基于气溶胶动力学和化学反应动力学,建立了化学气相淀积(CVD)反应器中普适动力学方程,导出了CVD反应器中超细颗粒粒径分布谱函数和薄膜淀积速率的计算方法;研究了操作参数对钛酸丁酯高温裂解过程中成核与成膜的影响.用成核与成膜竞争判据——H准数,研究了CVD反应器中成核与成膜的控制策略.     

有限元方法求解化学气相淀积反应器模型(Ⅱ)——热壁反应器模型及反应器中流动及传递过程的分析

分析了热壁化学气相淀积反应器在流型、温度和浓度分布以及淀积速率等方面与冷壁反应器的异同,探讨了流动特性、传递过程和反应器几何尺寸对淀积过程的影响,为淀积不同薄膜时反应器的选型及设计提供了方法和依据.     

CVD反应器中成膜与成核竞争机制的实验研究

利用管式热化学气相淀积反应器,研究了化学气相淀积过程中成核与成膜的竞争机制。结果表明,增加反应器操作压力、提高反应温度和反应物浓度,有利于粒子的生成而不利于薄膜淀积。在反应器中,淀积薄膜的表面形态各不相同。     

化学气相淀积反应器的化学工程分析和数学模型

化学气相淀积是在微电子、光纤通讯、超导等新技术领域里广泛用于制备各种具有特殊性能的薄膜的工艺过程。该过程的机理和气固相催化反应十分相似。本文以该过程在微电子器件生产中的应用为背景,概述了化学气相淀积的优点,分析了化学气相淀积反应器中传递过程和化学反应的相互关系,介绍了运用数学模型方法研究化学气相淀积反应器的进展。     

有限元方法求解化学气相淀积反应器模型(Ⅰ)——冷壁反应器模型及有限元解

建立了冷壁化学气相淀积反应器的数学模型,用Galerkin有限元方法对模型予以求解.计算中考虑了温度对物性参数的影响及自然对流因素,计算值和实验结果基本上一致.     

有限元方法求解化学气相淀积反应器模型(Ⅰ)——冷壁反应器模型及有限元解

建立了冷壁化学气相淀积反应器的数学模型,用Galerkin有限元方法对模型予以求解.计算中考虑了温度对物性参数的影响及自然对流因素,计算值和实验结果基本上一致.     

管式搅拌反应器中流动特性实验及模型研究

为进一步研究带机械搅拌装置的新型管式反应器内流动特性,采用刺激-响应技术,测定流体在不同操作条件下的停留时间分布(RTD)曲线并与无搅拌停留时间分布曲线作对比,计算了平均停留时间分布的统计特征值。用混合时间表征混合特性,用Peclet操作准数表征轴向扩散特性。结果表明,适当增大转速、流量或降低水位,都有利于反应器内流体的均匀混合。大体上随流量的减少和液位的升高停留时间有延长的趋势,转速变化对停留时间的影响不显著。在搅拌转速不超过400 r/min时,混合时间随着搅拌转速的增大而缩短。在实验范围内,反应器相当于3个串联全混槽反应器。     

双向层流反应器结构设计与膜层均匀性探讨

通过在线镀膜玻璃技术的研究,设计一种APCVD双向层流结构的反应器,其中进气腔设置不等宽流道,促进化学先驱气体扩散和反应沉积,从而提高了膜层均匀性。     

热管式固定床鼓泡反应器返混试验研究

为了研究热管式固定床鼓泡反应器的返混问题,采用脉冲法,在一内径为50mm、高800mm,床内充以多孔填料,内插一根16mm×2mm不锈钢-水热管的固定床反应器中,用并流向上的水和氮气进行返混试验研究。利用轴向扩散模型计算反应器轴向Peclet准数,考察了气相流速、液相流速、多孔介质和热管对返混的影响。研究表明反应器中热管的存在加重了返混。     

STEP COVERAGE PREDICTIONS USING COMBINED REACTOR SCALE AND FEATURE SCALE MODELS FOR BLANKET TUNGSTEN LPCVD

A reactor scale model (RSM) for a stagnation point, single wafer reactor for blanket tungsten LPCVD is used to calculate concentrations at the wafer surface. These concentrations and the wafer temperature, which is assumed to be measurable, are needed to determine the local tungsten deposition rate on the wafer and local film conformality (step coverage) in features on patterned wafers. Two feature scale models (FSMs) are used to determine step coverages in infinite trenches which have rectangular initial cross sections and an aspect ratio of five, as a function of reactor operating conditions; 1. a continuum-like diffusion-reaction model (DRM) for simultaneous Knudsen diffusion and heterogeneous surface reactions, and 2. a flux based model which includes ballistic transport of molecules and heterogeneous surface reactions (BTRM).|The RSM establishes “boundary conditions” for the feature scale models, by providing the flux of each species to the local wafer surface. Step coverages predicted using the FSMs with the reactant partial pressures at the wafer surface can be significantly lower than those predicted using reactant partial pressures at the reactor inlet, due to depletion of reactants. The flux based BTRM predicts higher step coverages than the DRM for the same wafer surface conditions.     

A new CVD reactor for semiconductor film deposition

The concept and design of a new chemical vapor deposition (CVD) reactor is presented for both epitaxial and nonepitaxial film deposition in semiconductor processing. The reactor is designed in such a way that a stagnant semiconductor source fluid of uniform concentration is provided for the film deposition without causing free or forced convection. The supply of the source gas for the deposition is by diffusion through a porous material such as quartz or graphite. Compared to the low pressure CVD (LPCVD) reactor with mounted wafer configuration, the new reactor should give a better film thickness uniformity and about an order of magnitude reduction in the amount of the source gas required. Further, at least for polycrystalline silicon deposition, the deposition rate can be much higher than is currently practiced with the LPCVD reactor. Design equations for the reactor are given. Details on the design for the polycrystalline silicon deposition are also given.     

Multivariable Optimal Learning Control of Wafer Temperatures in a Commercial RTP Equipment

A multivariable optimal iterative learning control technique called BMPC (Batch Model Predictive Control) has been implemented and evaluated in a commercial RTP (Rapid Thermal Processing) system fabricating 200 mm silicon wafers. The wafer temperature was controlled at multiple points along the radial direction by manipulating multiple tungsten‐halogen lamp groups. The study has addressed the following two issues: feasibility of BMPC in a commercial RTP equipment and enhancement of temperature uniformity using redundant inputs. As a consequence, satisfactory tracking performance could be realized with BMPC with reduced efforts for design and implementation of the controller by the standardized identification and tuning procedure. Redundant inputs whose number is larger than that of the temperature measurements was attempted to relieve the directionality of the system. Experimental tests revealed that the approach can provide us with improved temperature uniformity as well as tracking performance.     

连续刚度法对单晶硅片的力学性能的表征

利用纳米压痕仪通过连续刚度测量法对单晶硅片在压入过程中的接触刚度、硬度、弹性模量进行了连续测量.结果表明:当接触深度在20～32 nm左右时,单晶硅片的接触刚度与接触深度成直线关系,硬度和弹性模量基本保持不变,此时所测得的是单晶硅片表面氧化层的硬度和弹性模量,分别约为10.2 GPa和140.3 GPa.当接触深度在32～60 nm左右时,单晶硅片的接触刚度与接触深度成非直线关系,硬度和弹性模量随接触深度急剧增加,表明单晶硅片表面氧化层的硬度和弹性模量受到了基体材料的影响.当接触深度在60 nm以上时,单晶硅片的接触刚度与接触深度成直线关系,硬度和弹性模量基本保持不变,测得值为单晶硅的硬度和弹性模量,分别约为12.5 GPa和165.6 GPa.     

Mechanical Behavior of Diamond-Sawn Multi-Crystalline Silicon Wafers and its Improvement

Poor mechanical property is identified as a potential barrier to commercial development of diamond wire sawn multi-crystalline silicon wafers. 3-point bending tests of the diamond-sawn multi-crystalline silicon wafer samples, along with those of mono-crystalline silicon and of the slurry-sawn wafers for references, were carried out. The bending in two orthogonal orientations relative to the cutting marks was tested respectively. Critical strain at breakage is chosen to indicate the wafer’s strength against breakage in bending. Effective elastic moduli of the different wafer samples in bending were also measured. The results show that, compared to slurry-sawn silicon wafers, diamond-sawn silicon wafers, either of mono-crystalline or multi-crystalline, are stronger in the direction parallel to the cutting marks, and weaker in the direction vertical to the cutting marks; more importantly, for diamond-sawn multi-crystalline silicon wafers, a very low critical strain level, ～57 % of the slurry-sawn multi-crystalline silicon wafers, is identified, in their direction vertical to the cutting marks. In view of the relevance of the critical strain to the breakage rate for the main stream slurry-sawn wafers, this would cause an unacceptably high breakage rate in industrial production and application of the diamond-sawn multi-crystalline silicon wafers. Annealing was found to significantly raise the critical strains of various wafers, and encouragingly, annealing at temperature as low as 400 °C can raise the critical strain of the diamond-sawn multi-crystalline silicon wafers to a level similar to that of the slurry-sawn multi-crystalline silicon wafers.     

Scratch Fracture of Polycrystalline Silicon Wafers

Fracture of silicon wafers is responsible for lower than desirable manufacturing yields in the photovoltaic industry. This study investigates the fracture response of polycrystalline silicon wafers under sliding contacts at different length scales, by means of macro and microscratch tests which simulate cutting processes. The dominant fracture modes were found to be partial cone cracking (macro) and radial cracking (micro). Statistical analysis of the critical loads for crack initiation showed that polycrystalline wafers are weaker than their single‐crystal counterparts, that is, they crack at lower applied loads under comparable conditions. Moreover, the Weibull modulus of polycrystalline silicon was found to be the average of the relevant single‐crystal directions. Subsequent microscopic observations and flexure tests reveal that the lower resistance of polycrystalline silicon to scratch fracture is due mainly to the presence of relatively large polishing defects, and not to the weakness of its grain boundaries. Alternatives are proposed to minimize damage during ingot cutting, with a view to minimizing wafer breakages during wafer handling and machining.     

籽晶处理工艺对物理气相传输法生长SiC单晶的影响

将块体SiC单晶中切割下的晶片经研磨、抛光和腐蚀不同工艺处理后作为籽晶,用物理气相传输法生长SiC晶体,生长时间为10min。用光学显微镜观察晶片生长前后的形貌,讨论了不同处理工艺籽晶对晶体生长的影响。结果表明,研磨和抛光可以去除晶体切割时产生的凹坑和划痕,但残留的研磨变质层和抛光导致的机械损伤层可诱导晶片在高温晶体生长时产生多晶成核,腐蚀可以去除研磨和抛光时产生的机械损伤层,用腐蚀后的晶片作为籽晶,生长的晶体表面光滑,并且能够很好地复制籽晶的结构。     

Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon wafers

Diamond-on-insulator (DOI) wafers featuring ultrananocrystalline diamond are studied via atomic force microscopy, profilometer and wafer bow measurements. Plasma-activated direct bonding of DOI wafers to thermal oxide grown silicon wafers is investigated under vacuum. DOI wafer with chemical mechanical polishing (CMP) on the diamond surface makes a poor bonding to silicon wafers with thermal oxide. Our results show that plasma enhanced chemical vapor deposition of silicon dioxide on top of the DOI wafer, CMP of the oxide layer and annealing are essential to achieve very high quality direct bonding to thermal oxide grown on silicon wafers. Plasma activation results in the formation of high quality bonds without exceeding 550 °C in the direct wafer bonding process.     

Numerical analysis of LPCVD of SiO2 films from diethylsilane/oxygen

A mathematical model has been developed to explore the low pressure chemical vapor deposition (LPCVD) of silicon dioxide from diethylsilane (DES)/oxygen in a horizontal hot-wall reactor. We propose a new kinetic mechanism that includes realistic gas-phase and surface reactions. The partial differential equations in two-dimensional cylindrical coordinates are solved numerically by a control-volume-based finite difference method. The model successfully describes the behavior of the experimental data. Film growth rate and uniformity are studied over a wide range of operating conditions including deposition temperature, pressure, reactant flow rate, and distance between the inlet and the wafer. The predicted results show that parasitic gas-phase reactions become significant at higher pressures and temperatures resulting in a decrease in deposition rate. It is seen that the deposition rate becomes a maximum at the O₂/DES ratio of around 2.5. A temperature of 475‡C a pressure of 0.75 torr, and a total flow rate of 1,000 sccm are found to be desirable for obtaining both high deposition rate and good film uniformity.     

Iterative identification of temperature dynamics in single wafer rapid thermal processing

As the standard size of silicon wafers grows and performance specifications of integrated circuits become more demanding, a better control system to improve the processing time, uniformity and repeatability in rapid thermal processing (RTP) is needed. Identification and control are complicated because of nonlinearity, drift and the time-varying nature of the wafer dynamics. Various physical models for RTP are available. For control system design they can be approximated by diagonal nonlinear first order dynamics with multivariable static gains. However, these model structures of RTP have not been exploited for identification and control. Here, an identification method that iteratively updates the multivariable static gains is proposed. It simplifies the identification procedure and improves the accuracy of the identified model, especially the static gains, whose accurate identification is very important for better control.