Degradation of bipolar transistor current gain by hot holes duringreverse emitter-base bias stress

Experimental evidences are given which demonstrate that degradation of the common-emitter forward current gain h_FE of submicron silicon npn bipolar transistors at low reverse emitter-base junction applied voltage is caused by primary hot holes of the n⁺ /p emitter tunneling current rather than secondary hot electrons generated by the hot holes or thermally-generated hot electrons. Experiments also showed similar kinetic energy dependence of the generation rate of oxide/silicon interface traps by primary hot electrons and primary hot holes. Significant h_FE degradation was observed at stress voltages less than 2.4 V     

Identification of a corner tunneling current component in advancedCMOS-compatible bipolar transistors

A corner tunneling current component in the reverse-biased emitter-base junction of advanced CMOS compatible polysilicon self-aligned bipolar transistors has been identified by measuring base current as a function of temperature, bias voltage, and emitter shape. This current is found to be an excess tunneling current caused by an increase in defect density in the corners of the emitter and gives rise to three-dimensional effects in small-geometry devices. The devices used for this study were selected from batches aimed at optimizing the emitter-base system. For this reason, the starting material was n-type (~10¹⁶ cm^-3) and provided the collector regions of the transistors. The intrinsic base and lightly doped extrinsic base regions were both implanted at 30 keV to a dose of 1×10¹³ cm^-2. The activation anneal was performed at 1060°C for 20 s in a rapid thermal annealer. Under such conditions, the emitter-base junction is located about 600 Å below the polysilicon-substrate interface     

Analysis of CMOS transistor instabilities

A method for separation and calculation of gate oxide and surface state charges in CMOS transistors have been developed, leading to a significant improvement of the analysis of CMOS integrated circuit instabilities. In order to demonstrate the usefulness of the method, an analysis of instabilities in transistors subject to high electric field and high temperature-bias stress has been carried out. Four instability mechanisms associated with high electric field stress are observed. Successively we consider a positive gate oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps (in case of negative gate bias), electron tunneling from oxide electron traps into the oxide conduction band (in case of positive gate bias), and a surface state charge increase due to tunneling of electrons from the metal to the silicon (in case of negative gate bias) or from the silicon to the metal (in case of positive gate bias). In addition instabilities associated with high temperature-bias stress are observed: drift of mobile ions in the gate oxide, increase of positive trapped charge in the gate oxide and simultaneous increase of the surface state and negative gate oxide charges.     

Investigation of AlGaAs/GaAs superlattice-emitter resonanttunneling bipolar transistor (SE-RTBT)

A bipolar transistor with an i-Al_0.5Ga_0.5As/n⁺-GaAs superlattice emitter as both hole reflection barriers and electron tunneling barriers has been fabricated successfully. The AlGaAs/GaAs potential spike is eliminated by moving the heterointerface away from the emitter-base junction. Both the turn-on voltage of emitter-base and base-collector junctions are almost identical for the same current level. The room-temperature common-emitter current gain is over 60, and a collector-emitter offset voltage of 55 mV has been obtained with a base-to-emitter doping ratio of 10. Multiple differential negative resistance phenomena and different transistor operating regimes have been observed due to the tunneling effects in the AlGaAs/GaAs superlattice at 77 K. Calculated results are in agreement with experimental ones. Because of the existence of high peak-to-valley current ratios as well as current gain over 65, the SE-RTBT is suitable for multivalued logic circuit applications with relatively reduced complexity     

Impact of collector-base junction traps on low-frequency noise in high breakdown Voltage SiGe HBTs

This work investigates the impact of collector-base (CB) junction traps on low-frequency noise in high breakdown voltage (HBV) SiGe HBTs. By comparing the base current and 1/f noise at the same internal emitter-base (EB) voltage of the standard breakdown voltage (SBV) and HBV devices, we show that the CB junction traps not only increase base current, but also contribute base current 1/f noise when high injection occurs. The individual 1/f noise contributions from the emitter-base junction traps and from the collector-base junction traps are separated. The dependence of the 1/f noise component on the corresponding base current component is determined, and shown to be different for the EB and CB junction traps. The dependence of the total 1/f noise on the total base current, however, remains the same before and after high injection occurs in the HBV device, which is approximately the same as that for the SBV device. The I/sub B/ contribution from the CB junction recombination current needs to be modeled for accurate I-V and 1/f noise modeling.     

MOSFET degradation due to stressing of thin oxide

Oxide and interface traps in 100 Å SiO2created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V, and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at sufficiently high fluence, it becomes negative due to the trapping of electrons with a centroid of 60 Å from the injector (cathode) interface. Interface traps (Surface states) are created by tunneling electrons flowing to and from the substrate. The interface-trap energy distribution gives a distinct peak at 0.65 eV above the valence band edge. The positive charge trapping and interface traps generation saturate at high electron fluence, but not the electron trap generation. The generation rates for electron traps and interface traps are weak functions of tunneling current density over the range tested. The interface traps cause degradations in subthreshold current slope and surface electron mobility. The threshold-voltage shift can be either positive or negative under the combined influence of the oxide charges and the interface charges.     

Avalanche degradation of hFE

Degradation of low current hFEas a result of avalanching the emitter-base junction of a silicon planar transistor is shown to be explinable by an increase in surface recombination velocity within the vicinity of the emitter-base metallurgical junction. This degradation mechanism manifests itself on a gate-controlled transistor by an additional peak in the plot of base current versus gate voltage. The magnitude as well as the "width" of this peak can be accounted for theoretically by assuming a given emitter-base impurity gradient and a localized increase in surface recombination velocity in and around the metallurgical junction. Experimental evidence is also presented for localized charge trapping within the oxide over the emitter-base junction as a result Of avalanching under an applied field.     

Mechanisms of interface trap-induced drain leakage current inoff-state n-MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO₂ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 μm n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V_dg). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression ΔI_d=Aexp(B_it/F). The value of B_it about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V_dg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V_dg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant     

Modeling of SILC based on electron and hole tunneling. I. Transienteffects

A detailed investigation of the steady-state and transient leakage currents in thin oxides is proposed. The experimental data are compared with numerical results obtained from a model based on an inelastic trap-assisted tunneling process, which includes both electron and hole contributions. In order to accurately reproduce the transient discharge currents, a continuous distribution of oxide traps was adopted. The energies of these levels can be either in correspondence of the conduction or valence band edges of the adjacent silicon/polysilicon layers. Both electrons and holes contribute to the transient stress-induced leakage current (SILC), but the extracted trap densities cannot account for the steady-state SILC. A different mechanism, involving trap levels with energy aligned to the energy gap of the silicon layers is proposed and is developed in the following paper. The model can be applied to any type of device and bias conditions and may be used to correctly recognize the role of electron and hole SILC and the spatial and energy distribution of defect states     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

Emitter avalanche currents in gated transistors

The creation of interface states and the trapping of charge in the oxide during avalanche breakdown of the emitter-base (e-b) junction of planar transistors was studied. Two types of n-p-n transistors, differing in the amount of boron in the base region, were investigated. The creation of interface states was largest in the transistors with a higher concentration of boron in the base region, probably due to a higher density of avalanche plasma near the Si-SiO2interface. The amount of negative charge trapped in the oxide during breakdown with a positive voltage applied to a field plate above the e-b junction was found to be related to the magnitude of the current through the oxide during breakdown. This current is obviously due to hot electrons injected into the oxide. A fraction of these electrons is trapped with about the same efficiency in both types of transistors.     

Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

Recombination centers in silicon transistor emitter-base junctions

Analysis of the temperature dependence of silicon transistor emitter-base junction forward characteristics has yielded information about the recombination centers that give rise to the "non-ideal" component of the base current. The recombination centers are either slightly above midgap with electron capture cross-section much larger than hole capture cross-section, or slightly below midgap with hole capture cross-section much larger than electron capture cross-section.     

Hot-carrier-stress effects on gate-induced drain leakage current inn-channel MOSFETs

The effects of hot-carrier stress on gate-induced drain leakage (GIDL) current in n-channel MOSFETs with thin gate oxides are studied. It is found that the effects of generated interface traps (ΔD _it) and oxide trapped charge on the GIDL current enhancement are very different. Specifically, it is shown that the oxide trapped charge only shifts the flat-band voltage, unlike ΔD _it. Besides band-to-band (B-B) tunneling, ΔD _it introduces an additional trap-assisted leakage current component. Evidence for this extra component is provided by hole injection. While trapped-charge induced leakage current can be eliminated by a hole injection subsequent to stress, such injection does not suppress interface-trap-induced leakage current     

Small offset-voltage In0.49Ga0.51P/GaAsdouble-barrier bipolar transistor

In_0.49Ga_0.51P/GaAs double-barrier bipolar transistors (DBBTs) grown by gas-source molecular beam epitaxy (GSMBE) have been fabricated and measured. This structure has two InGaP barrier layers (100 Å in thickness): one is inserted between the emitter-base (e-b) junction and the other between the base-collector (b-c) junction. An offset voltage of 26 mV and a differential current gain of 120 at room temperature were obtained with a heavily doped p⁺ (2×10¹⁹ cm^-3) base (500 Å in thickness). The small offset voltage was attributed to the similar structure of the e-b and b-c junctions and to the suppression of the hole injection current into the collector by the InGaP hole barrier at the b-c junction     

Recovery of the NBTI-Stressed Ultrathin Gate p-MOSFET: The Role of Deep-Level Hole Traps

Under a static negative-bias temperature stress, the negative threshold-voltage V_t shift (extracted from the dc current-voltage characteristic) of the direct-tunneling gate p-MOSFET is found to be substantially larger than that calculated based on the interface-state density measured using the charge-pumping method. Device-recovery characteristics from bipolar gate stress show that interface states alone cannot entirely account for the V_t shift, and indicate that a substantial number of positive oxide charges are also generated during stress. Stability of the increased V_t shift under a negative dc gate biasing and unipolar ac gate pulsing implies that these positive charges are deep-level hole traps with energy states above the Si conduction band edge. Because the defect states are outside the energy window of direct electron tunneling, their long relaxation time plays an important role in the slow recovery transient of the p-MOSFET     

Si hetero-bipolar transistor with a fluorine-doped SiC emitter anda thin, highly doped epitaxial base

The effect of fluorine doping on SiC/Si heterojunction bipolar transistors (HBTs) is studied. The film properties of the fluorine-doped SiC and device characteristics of an HBT using the SiC emitter and a 50-nm-thick, highly doped epitaxial base (10¹⁹/cm³) are presented. The current gain is improved from 15 to 80 by doping with fluorine. The current gain is four times larger than that of a conventional poly-Si emitter homo-transistor with the same base structure. In spite of the very thin base, the Early voltage is over 100 V. Forward-bias tunneling current was hardly seen at the emitter-base junction. The fluorine appears to terminate the dangling bonds. The results show the possibility of fabricating transistors with a very thin, highly doped base     

Characterization, modeling, and minimization of transient thresholdvoltage shifts in MOSFETs

MOSFETs subjected to large-signal gate-source voltage pulses on microsecond to millisecond time scales exhibit transient threshold voltage shifts which relax over considerably longer periods of time. This problem is important in high-accuracy analog circuits where it can cause errors at the 12 b level and above. In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length. In contrast to previous studies, threshold voltage shifts are measured at time and voltage scales relevant to analog circuits, and are shown to occur even when the effects of Fowler-Nordheim tunneling, avalanche injection, hot carriers, trap generation, self-heating, mobile ions, and dipolar polarizations are absent. A new model is proposed in which channel charge carriers tunnel to and from near-interface oxide traps by one of three parallel pathways. Transitions may occur elastically, by direct tunneling between the silicon band edges and an oxide trap, or inelastically, by tunneling in conjunction with a thermal transition in the insulator or at the Si-SiO₂ interface. Simulations based on this model show excellent agreement with experimental results. The threshold voltage shifts are also shown to be correlated with 1/f noise, in corroboration of the tunneling model. Techniques for the minimization and modeling of errors in circuits are presented     

Oxide-Trapped Charges Induced by Electrostatic Discharge Impulse Stress

The characteristics of oxide-trapped charges Q_ot induced by electrostatic discharge high-field current impulse stress, i.e., transmission line pulsing (TLP), were studied. It was observed that for a 3.2-nm-thin oxide, the centroid evolution and the critical density of positive oxide-trapped charges Q_ot ⁺ to trigger oxide breakdown are about the same between dc and TLP impulse stresses. These results are consistent with the existing models of stress-induced trapping charges and hole-induced oxide breakdown. However, different behaviors of Q_ot and centroid were found for 14-nm-thick oxides subjected to different stress tests. TLP impulse stress generates far less amount of negative oxide- trapped charges Q_ot ^- than dc stress, and the positive oxide-trapped charges finally dominate over the negative oxide-trapped charges. This impulse stress imposes a high density and transient current on the oxide, which induces traps at the tunneling distance locally. The hotter injected electrons generate more efficient hole trappings to provoke breakdown with lower density of oxide-trapped charges in comparison with dc stress test.     

Characterization of various stress-induced oxide traps in MOSFET'sby using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant