金属纳米晶快闪存储器研究进展

金属纳米晶具有态密度高、费米能级选择范围广以及无多维载流子限制效应等优越性,预示着金属纳米晶快闪存储器在下一代闪存器件中具有很好的应用前景。从金属纳米晶存储器的工作原理、纳米晶的制备方法、以及新型介质材料和电荷俘获层结构等方面,对金属纳米晶存储器近年来的研究进展进行了总结。     

金属诱导横向晶化非晶硅薄膜技术及新发展

金属诱导横向晶化技术(MILC)由于具有晶化温度低、晶化颗粒大等优点而获得了快速发展。阐述了金属诱导横向晶化非晶硅薄膜的晶化机理、晶化效果及影响晶化效果的主要参数,并介绍了基于多种辅助措施,如离子掺杂、电磁场辅助、微波退火、激光退火、氮硅化合物覆盖法和焦耳热升温法等方法,以优化金属诱导横向晶化非晶硅薄膜。辅助措施均有利于增强晶化效果,更易获得大面积无孪晶多晶硅薄膜,并具有较高的载流子迁移率。最后提出采用微纳金属阵列结构调控晶化能量,实现低温、高速、大晶粒直径的多晶硅薄膜制备新方法。     

基于不同测量手段的纳米晶器件的存储特性

对纳米晶器件,尤其是MOS电容进行了横截面TEM分析和不同条件下的电学特性(C-V特性)测量,包括 /-BT分析. 揭示了系统的纳米晶存储物理机制,例如电荷俘获、界面态填充和温度特性. 研究结果表明,高温、大电压摆幅和偏置情况下,器件编程窗口的恶化和阈值电压的漂移与多数载流子的种类有关.     

硅纳米晶存储器的耐受性研究

首先介绍了硅纳米晶粒的制备工艺以及硅纳米晶存储器件的基本特性。接着重点探讨了硅纳米晶存储器耐久性退化的物理机制,发现应力引起的界面陷阱是耐受性退化的主要原因。随后,同时采用多种分析手段,如电荷泵法和CV曲线分析法对界面陷阱的退化机理进行了更深入细致的研究。从界面陷阱在禁带中的能级分布中发现,相较于未施加应力时界面陷阱的双峰分布,施加应力后产生了新的Pb1中心的双峰。最后,分别从降低擦写电压和对载流子预热的角度提出了三种新的编程方法,有效提高了硅纳米晶存储器件的耐受性。     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

掺铒对激光烧蚀制备纳米硅晶薄膜形貌的影响

在2×10-4 Pa真空下，采用XeCl准分子激光器(波长308 nm)，调整激光单脉冲能量密度为3 J/cm2，交替烧蚀高纯单晶硅(Si)靶和铒(Er)靶，通过调整辐照两靶的激光脉冲个数比来控制掺Er浓度，分别在Si衬底和石英衬底上制备了掺Er非晶Si薄膜。在N2气保护下经高温热退火实现纳米晶化，退火时间为30 min。采用扫描电子显微镜(SEM)观察所得到的样品的表面形貌显示，铒掺杂影响着薄膜的表面形貌，与不掺Er情况相比，掺入适量的Er可以在较低的退火温度下得到晶粒尺寸分布更均匀的薄膜;拉曼谱的测量结果表明，在相同的退火温度下，Er的掺入有利于晶粒的长大，但同时降低了薄膜的晶化度，掺Er非晶Si薄膜要实现完全晶化需要更高的退火温度。     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

Ni金属诱导晶化非晶硅(a-Si:H)薄膜

对在氢化非晶硅薄膜（a-Si：H）上溅射金属Ni的样品进行金属诱导晶化（MIC）／金属诱导横向晶化（MILC），制备多晶硅薄膜（p-Si）的上艺及薄膜特性进行了研究。XRD测最结果表明非晶硅在500℃退火1h后就已经全部晶化。金属诱导晶化的优选晶向为（220）．而且晶粒随退火时间的延长而长大。非晶硅薄膜样品500℃下退火6h后的扫描电镜照片显示，原金属镍覆盖区非晶硅全部晶化．晶粒均匀．平均晶粒大小约为0．3μm，而且已经发生横向晶化。EDS测试Ni在晶化的非晶硅薄膜中的原子百分含量分析表明，金属Ni在MILC过程中的作用只是催化晶化．除了少量残留在MILC多晶硅中外．其余的Ni原子都迁移至晶化的前沿。500℃下退火20h后样品的Raman测试结果也表明．金属离子向周边薄膜扩散．横向晶化了非晶硅薄膜。     

用化学镀方法在不同衬底上制备纳米尺度金属插塞电极的研究

纳米尺度金属插塞电极在现代纳米电子学中有很重要的应用价值。本文研究了用化学镀方法制备纳米尺度金属插塞电极,具有简单、低成本和自选择性的优点。化学镀甚至可以分别在硅衬底、钨衬底和氮化钛衬底上制备出直径小于50纳米的镍插塞电极。用能量色散X射线微量分析仪（EDXM）测定出用化学镀在硅衬底上制备出的纳米尺度插塞电极的主要成分是镍。最后,采用化学镀方法,制备了直径为9微米的插塞电极的垂直结构相变存储器器件。通过研究器件的电流-电压特性表明,化学镀方法可以满足器件应用要求。因此,用简单、低成本的化学镀方法来制备纳米尺度金属插塞电极,对器件的应用有重要意义。     

A novel low-temperature method of SiO2 film deposition forMOSFET applications

Silicon dioxide dielectric films were deposited at low temperatures (250–300°) using a novel plasma enhanced MO-CVD process. In this process, the substrate was kept remote from the plasma region and the deposition of the film was achieved at low pressure (0.8-1.0 Torr) and low dc plasma power (0.3 W· cm⁻²). Films deposited using tetraethyloxysilane (TEOS) and nitrous oxide (N₂O) as reactant material had, under optimum deposition conditions, resistivities of ≥ 10¹⁵ ohm-cm, a refractive index of 1.46, a dielectric constant of 3.98 and a breakdown field strength ≥ 5x 10₆ V·cm⁻¹. AES and SIMS analysis indicated that the films were of high purity and were stoichiometric with no metallic silicon present. MOS-capacitors fabricated on Si-substrates showed no hysteresis and no frequency dispersion of capacitance in the accumulation region. An interface state density in the range of 10¹¹ cm⁻²eV⁻¹ was achieved for these MOS devices using our deposited SiO₂dielectric films.     

Carrier transport and related phenomena in MOS devices

Silicon-based devices are currently the most attractive group because they are functioning at room temperature and can be easily integrated into conventional silicon microelectronics. There are many models and simulation programs available to compute CV curves with quantum correction [Choi C-H, Wu Y, Goo JS, Yu Z, Dutton RW. IEEE Trans on Electron Devi 2000; 47(10): 1843; Croci S, Plossu C, Burignat S. J Mater Sci Mater Electron 2003; 14: 311; Soliman L, Duval E, Benzohra M, Lheurette E, Ketata K, Ketata M. Mater Sci Semicond Process 2001; 4: 163]. This work deals with the simulation of electron transfer through SiO₂ barrier of metal–oxide–semiconductor structure (MOS). The carrier density is given by a self consistent resolution of Schrödinger and Poisson equations and then the MOS capacitance is deduced and compared with results available in literature. As it is well known, the MOS capacitance–voltage profiling provides a simple determination of structure parameters. The extracted tunnel oxide thickness and substrate doping are compared with those used in the simulation. For the purpose to investigate the electron tunnelling through the barrier, we have used the transfer matrix approach. Using I–V simulations, we have shown that the traps in SiO₂ matrix have a drastic influence on electron tunnelling through the barrier. The trap-assisted contribution to the tunnelling current is included in many models [Maserjian J, Zamani N. J Appl Phys 1982; 53(1): 559; Houssa M, Stesmans A, Heyns MM. Semicond Sci Technol 2001; 16: 427; Aziz A, Kassmi K, Kassmi Ka, Olivie F. Semicond Sci Technol 2004; 19: 877; Wu You-Lin, Lin Shi-Tin. IEEE Trans Dev Mater Reliab 2006; 6(1): 75; Larcher L. IEEE Trans Electron Dev 2003; 50(5): 1246]; this is the basis for the interpretation of stress induced leakage current (SILC) and breakdown events. Memory effect becomes typical for this structure. We have studied the I–V dependence with trap parameters.     

Analytic approximation of the jitter incurred by CBR traffics in IP networks

In this paper, an analytic approximation is derived for the end-to-end delay-jitter incurred by a periodic traffic with constant packet size. The single node case is considered first. It is assumed that the periodic traffic is multiplexed with a background packet stream under the FCFS service discipline. The processes governing the packet arrivals and the packet sizes of the background traffic are assumed to be general renewal processes. A very simple analytical approximation is derived and its accuracy is assessed by means of event-driven simulations. This approximation is then extended to the multiple node case yielding a simple analytical approximation of the end-to-end jitter. This approximation is shown to be fairly accurate in the light to moderate traffic conditions typically encountered in IP core networks.     

Low-Power FPGA-Implementation of <Emphasis Type="Italic">atan</Emphasis>(<Emphasis Type="Italic">Y</Emphasis>/<Emphasis Type="Italic">X</Emphasis>) Using Look-Up Table Methods for Communication Applications

This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC or 46% lower than multipartite approach.

New op-amp-RC to G m -C transformation method

A new transformation method is proposed and used to transform op-amp-RC circuits to G _m -C ones with only grounded capacitors. The proposed method enables the generation of high-performance G _m -C filters that benefit from the advantages of good and well-known op-amp-RC structures and at the same time feature electronic tunability, high frequency capability and monolithic integration ability. An attractive feature of the proposed method is that it results in G _m -C structures with only grounded capacitors in spite of the presence of floating capacitors in the original op-amp-RC circuits. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA, U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr. Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr. Soliman gave a lecture at Nanyang Technological University, Singapore. Dr. Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr. Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr. Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr. Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004–Now.     

Stress in “cathodic” plasma oxides as a function of processing parameters

Stress in SiO₂ films grown via a “cathodic” plasma oxidation process has been examined as a function of growth and processing conditions. The total stress for oxides grown at 350° C in either 85% Ar/15%O₂ or 100% O₂ ambients at 700 W, 4 MHz, and a total pressure of 80 mTorr was found to be identical. It was observed that annealing these oxides for 24 hr at 700° C in an ultra-pure oxygen ambient did not have any effect on the electrical properties, but that the stress did increase slightly. Electrical properties were measured on MOS capacitors, specifically focusing on net fixed oxide charge and breakdown strength. In addition, both as-grown and annealed samples were subjected to 8.5 × 10⁶ rad(SiO₂) Al K_α ionizing radiation to simulate exposure to X-ray lithography. Notwithstanding the generation of a large areal density of net coulombic charge in the insulator, the presence of these defects did not cause a measurable change in the interfacial stress level. Surprisingly, it was found that about 16% of the wafers plastically deformed during oxide growth at 350° C and about 35% of the wafers were found to be deformed after annealing of the oxides at 700° C. Dry, thermal oxides grown at 700° C were seen to possess similar electrical properties but exhibited a higher stress than the plasma oxides.     

Construction of Time-Relaxed c-Broadcast Networks

C-broadcasting is an information dissemination task where a message, originated at any node in a network, is transmitted to all other nodes with the restriction that each node having the message can transmit it to almost c neighbors simultaneously. If the transmission time of the message is set to be one time unit, a minimal c-broadcast network (c-MBN) is a communication network in which c-broadcasting from any node can be accomplished in log _c+1 n time units, where n is the number of nodes and log _c+1 n is the fastest possible broadcast time. If networks are sparse, additional time units may be required to perform c-broadcasting. A time-relaxed c-broadcast network, denoted as (t,c)-RBN, is a network where c-broadcasting from any node can be completed in log _c+1 n+t time units. In this paper, a network compounding algorithm is proposed to construct large sparse (t,c)-RBNs by linking multiple copies of a time-relaxed network of small size using the structure of another time-relaxed network. Computational results are presented to show the effectiveness of the proposed algorithm.     

Comparison of <Emphasis Type="Italic">p</Emphasis>-cycles and <Emphasis Type="Italic">p</Emphasis>-trees in a unified mathematical framework

As high-speed networks grow in capacity, network protection becomes increasingly important. Recently, following interest in p-cycle protection, the related concept of p-trees has also been studied. In one line of work, a so-called “hierarchical tree” approach is studied and compared to p-cycles on some points. Some of the qualitative conclusions drawn, however, apply only to p-cycle designs consisting of a single Hamiltonian p-cycle. There are other confounding factors in the comparison between the two, such as the fact that, while the tree-based approach is not 100% restorable, p-cycles are. The tree and p-cycle networks are also designed by highly dissimilar methods. In addition, the claims regarding hierarchical trees seem to contradict earlier work, which found pre-planned trees to be significantly less capacity-efficient than p-cycles. These contradictory findings need to be resolved; a correct understanding of how these two architectures rank in terms of capacity efficiency is a basic issue of network science in this field. We therefore revisit the question in a definitive and novel way in which a unified optimal design framework compares minimum capacity, 100% restorable p-tree and p-cycle network designs. Results confirm the significantly higher capacity efficiency of p-cycles. Supporting discussion provides intuitive appreciation of why this is so, and the unified design framework contributes a further theoretical appreciation of how pre-planned trees and pre-connected cycles are related. In a novel further experiment we use the common optimal design model to study p-cycle/p-tree hybrid designs. This experiment answers the question “To what extent can a selection of trees compliment a cycle-based design, or vice-versa?” The results demonstrate the intrinsic merit of cycles over trees for pre-planned protection.     

dV/dt对IPM中IGBT栅极电路的影响分析

The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment.It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT.The dV/dt rate,gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike.The device with a higher dV/dt rate,gate-collector capacitance,gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on.By optimizing these parameters,the dV/dt induced voltage spike can be effectively controlled.     

Comments on “Reliability and component importance of a consecutive-k-out-of-n system” by Zuo

Zuo claimed that the comparison of Birnbaum importance between two components for a consecutive-k-out-of-n:G system is the same as that for the F-system. We show that this is not the case and give a correct relation between the two systems.