Timing circuits for RSFQ digital systems

A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm². The most complex clock controller generates trains of 2²⁴ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6×10^-5 . The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz     

Parallel vector processing of multidimensional orthogonal transforms for digital signal processing applications

This paper presents vector and parallel algorithms and implementations of one- and two-dimensional orthogonal transforms. The speed performances are evaluated on Cray X-MP/48 vector computer. The sinusoidal orthogonal transforms are computed using fast real Fourier transform (FFT) kernel. The non-sinusoidal orthogonal transform algorithms are derived by using direct factorizations of transform matrices. Concurrent processing is achieved by using the multitasking capability of Cray X-MP/48 to transform long data vectors and two-dimensional data vectors. The discrete orthogonal transforms discussed in this paper include: Fourier transform (DFT), cosine transform (DCT), sine transform (DST), Hartley transform (DHT), Walsh transform (DWHT) and Hadamard transform (DHDT). The factors affecting the speedup of vector and parallel processing of these transforms are considered. The vectorization techniques are illustrated by an FFT example.This work is supported in part by the National Science Foundation, Pittsburgh Supercomputing Center (grant number ECS-880012P) and by the PEW Science Education Program.     

RSFQ logic/memory family: a new Josephson-junction technology forsub-terahertz-clock-frequency digital systems

Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output latch (register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology     

基于光学向量矩阵乘法器的光学信息处理系统研究

光学向量-矩阵乘法器(OVMM)作为一种利 用光学方式进行向量-矩阵运算(VMM)的光学系统,由于采用天然具有高带宽、高并行性的 光学处理方式, 在海量数据处理领域极具潜力。本文实现了一套基于空间OVMM的光电混合 数字信号处理系统,采用自主设计实现的维度为16×16的空间OVMM作 为核心运算单元。实验结果显示,系统能够完成76.8G/s乘法累加 (MAC)运算,满足实时 数据处理对运算速度的需求。系统使用可编程逻辑器件(FPGA)作为电学协处理单元的核心组 成部分,因此具有可编程性,可以满足多种不同的应用需求。     

RSFQ circuitry realized in a SINIS technology process

We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor-insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j_C=400 A/cm² and a characteristic voltage of V_C=165 μV, the area of the smallest junction is A=24 μm². The junctions exhibit nearly hysteresis-free current-voltage characteristics (hysteresis: less than 7%), the intra-wafer parameter spread for j_C is below ±8%. The margins of the bias current I_b of the circuits have been experimentally determined and found to be larger than ±24%. At preset, constant values of I_b, the range of a separate bias current I_bsw fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than ±56%     

数字滤波器在数字信号处理中的应用设计

在信号处理中,滤波占有十分重要的地位.数字滤波是数字信号处理的基本方法,以FIR滤波器为基础,利用MATLB程序设计语言对低通FIR数字滤波器进行了有效的设计,应用DSP 汇编语言编程实现了该滤波器.     

Bit error rate experiments in ring-shaped RSFQ circuits

Ring-shaped rapid single flux quantum (RSFQ) circuits composed of segments of Josephson transmission lines (JTLs) and other RSFQ circuits enable permanent SFQ pulse circulation. New ring structures of different designs have been realized which comprise T-flipflop (TFF) and multiplier (MULT) circuits. Reliability in circuit operation has been proven experimentally by a bit error rate BER≅10⁻¹⁶. The fabrication process has been optimized by using PTB-4 μm Nb/Al₂O₃–Al/Nb trilayer technology with externally shunted tunnel junctions of critical current densities of j_c=≅1 kA/cm². Characteristic voltage is V_c=250 μV and Steward–McCumber parameter β_c≤1. A linear dependence of pulse circulation frequency on JTL bias currents has been measured within a bias current interval of 20%.     

Soft digital signal processing

In this paper, we propose a framework for low-energy digital signal processing (DSP), where the supply voltage is scaled beyond the critical voltage imposed by the requirement to match the critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noise-tolerance (ANT) schemes. The resulting setup that comprises of the DSP architecture operating at subcritical voltage and the error control scheme is referred to as soft DSP. The effectiveness of the proposed scheme is enhanced when arithmetic units with a higher "delay imbalance" are employed. A prediction-based error-control scheme is proposed to enhance the performance of the filtering algorithm in the presence of errors due to soft computations. For a frequency selective filter, it is shown that the proposed scheme provides 60-81% reduction in energy dissipation for filter bandwidths up to 0.5 π (where 2 π corresponds to the sampling frequency f_s) over that achieved via conventional architecture and voltage scaling, with a maximum of 0.5-dB degradation in the output signal-to-noise ratio (SNR_o). It is also shown that the proposed algorithmic noise-tolerance schemes can also be used to improve the performance of DSP algorithms in presence of bit-error rates of up to 10^-3 due to deep submicron (DSM) noise     

Fundamental limits in digital information processing

Computing and information processing are limited by a variety of factors. Some of these, such as the need to dissipate energy, the high voltage requirement, and the difficulty of removing heat are fundamental in that they have a basis in physical theory and in knowledge of the properties of materials. Limits arising from the physics of devices are also in this class. It appears that many of these physical limits could be relaxed by operating circuits at low temperature. Another class of limits is based on the experiences of many independent workers who find that a large amount of communication among various parts of a system is required. The many long interconnections utilized create great complexity and play a dominant role in the power dissipation required in information processing.     

Sub-word parallelism in digital signal processing

We deal with parallelism at the data level. We describe an implementation of the architectural technique called sub-word parallelism (SWP), which increases parallelism at the data-element-level by means of partitioning a processor's data path. The specific implementation we focus on is based on the TigerSHARC DSP architecture, developed at Analog Devices, Inc. As a result of SWP, the same data path and computation units perform more than one computation on an N-element composite word. This composite word consists of more than one adjacent sub-words. SWP is quite common and exists in production versions of most major general-purpose microprocessors. We also present an implementation of an FIR filter in the TigerSHARC using data-level SWP as an example     

Signal processing in digital fiber communications

Transmission of pcm signals over optical fibers is limited in transmission rate by the inherent imperfections of the carrier medium. The paper discusses the model for an optical telecommunications system (signal and noise models), simulation in base-band (stressing the rational approximation made for the fiber’s transfer function) pulse equalization, encoding and synchronization. Equalizers, whether linear or not, recursive or not, adjustable or not, reduce intersymbol interference, by compensation of distortion in compliance with certain criteria with a view to improving the error rate. The encoding used is a trade-off between bandwidth, tolerance to intersymbol interference and acquisition and tracking of the signal.     

Order statistics in digital image processing

A family of nonlinear filters based on order statistics is presented. A mathematical tool derived through robust estimation theory, order statistics has allowed engineers to develop nonlinear filters with excellent robustness properties. These filters are well suited to digital image processing because they preserve the edges and the fine details of an image much better than conventional linear filters. The probabilistic and deterministic properties of the best known and most widely used filter in this family, the median filter, are discussed. In addition, the authors consider filters that, while not based on order statistics, are related to them through robust estimation theory. A table that ranks nonlinear filters under a variety of performance criteria is included. Most of the topics treated are very active research areas, and the applications are varied, including HDTV, multichannel signal processing of geophysical and ECG/EEG data, and a variety of telecommunications applications     

Design and testing of data-driven self-timed RSFQ shift register

We report design, implementation and testing of a superconductive rapid single flux quantum (RSFQ) shift register based on a data-driven self-timed (DDST) architecture, and demonstrated the validity of this asynchronous design approach. In the DDST architecture, a clock signal is localized within the basic modules, and complementary data signals are used between the modules to transmit timing information. A larger system is simply an array of the basic modules and no extra timing consideration is required. Monte Carlo analysis on a 4-bit DDST shift register has shown that a 40-kbit shift register operating at 20 GHz can be built by using the present Nb Josephson technology. We have observed fully correct operation of a cascade of two 4-bit DDST shift registers with dc bias voltage margin of ±15% at low frequency and ±10% at 20 GHz.     

Data-driven multicomputers in digital signal processing

New technologies of integration allow the design of powerful systems which may include several thousands of elementary processors. These multiprocessors may be used for a range of applications in signal and data processing. However, assuring the proper interaction of a large number of processors and the ultimate safe execution of the user programs presents a crucial scheduling problem. The scheduling of operations upon the availability of their operands has been termed the data-driven mode of execution and offers an elegant solution to the issue. This approach is described in this paper and several architectures which have been proposed or implemented (systolic arrays, data-flow machines, etc.) are examined in detail. The problems associated with data-driven execution are also studied. A multi-level approach to high-speed digital signal processing is then evaluated.     

High-speed digital signal processing and control

An attempt is made to organize and survey recent work, and to present it in a unified and accessible form. The need for a new approach suitable for high-speed processing is discussed in the context of several applications in control and communications, and a historical perspective of the use of difference operators in numerical analysis is presented. The general systems calculus, based on divided-different operators is introduced to unify the continuous-time and discrete-time systems theories. This calculus is then used as a framework to treat the three problems of system state estimation; system identification and time-series modeling; and control system design. Realization aspects of algorithms based on the difference operator representation, including such issues as coefficient rounding and implementation with standard hardware, are also discussed     

数字信号处理及DSP芯片的发展前景

简要介绍了DSP的设计流程及其实现方法,着重介绍了DSPs芯片结构特点、运算速度、应用与市场,并展望了DSPs芯片的发展前景。     

The latest word in digital and media processing

The article discusses the technology behind the resurgence of DSP oriented microprocessors and the techniques that allow one to use them well. After an overview of the VLIW architecture, it discusses three main areas: VLIW architectural feature relevant to DSP applications; their associated complier techniques; and coding techniques that allow the application programmer, while still coding in a high-level language, to best exploit the architecture