A Novel Hybrid Phase-Locked-Loop Frequency Synthesizer Using Single-Electron Devices and CMOS Transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PLL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PLL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.     

单电子存储器

介绍了单电子存储器的发展情况和几种单电子存储器的基本特性,并将库仑阻塞效应作为存储器工作的理论基础进行了讨论。随着传统存储器集成度的不断提高,每个存储单元的电子数目不断减少,并逐渐接近其极限,使传统存储器的发展面临困难。采用单电子存储器有望解决这个困难,它们通常具有单个量子点或者是多隧穿结结构,存储一个比特的信息只需要精确控制增加或者减少一定数目的电子就可以实现。单电子器件的工作通常只需要很少的电子甚至一个电子就可以实现,具有高速和低功耗的特点,因此可以实现信息超高密度存储。与单电子逻辑电路相比,单电子存储器更容易解决随机背景电荷涨落的问题,因此从实际应用的角度来看,单电子存储器的应用前景更为光明。     

基于控阈技术的电流型CMOS全加器的通用设计方法

利用电流信号的阈值易于控制这一特点,对电流型CMOS电路中如何实现阈值控制进行了研究.以开关信号理论为指导,建立了实现阈值控制电路的电流传输开关运算并具体指导设计了具有阈值控制功能的二值和多值电流型CMOS全加器.提出了适用于任意逻辑值的可控阈电流型CMOS全加器的通用设计方法.通过对开关单元实施阈值控制后,所设计的电路在结构上得到了非常明显的简化,在性能上也获得了改善.最后给出了采用0.25μm CMOS工艺参数的HSPICE模拟结果及其能耗比较.     

Novel Power-Delay-Area-Efficient Approach to Generic Modular Addition

Modular adders are fundamental arithmetic components typically employed in residue number system (RNS)-based digital signal processing (DSP) systems. They are widely used in modular multipliers and residue-to-binary converters and in implementing other residue arithmetic operations such as scaling. In this paper, a methodology for designing power-delay-area-efficient modular adders based on carry propagate addition is presented. The binary representational characteristics of the modulus are exploited to allow the sharing of hardware in a fast modular adder topology. VLSI implementation results using 0.13- standard-cell technology, together with a theoretical analysis, show that this approach produces adders that offer efficient tradeoffs when compared with the fastest through to the smallest generic modular adders in the literature.     

Current-mode CMOS multiple-valued logic circuits

Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described     

Comparative analysis of CMOS adders circuits based on 10 transistors

Development of digital signal processing devices has led to appearance of a series of CMOS circuit designs of arithmetic and logic blocks with a small number of transistors. In this paper we suggest a classification of full single-bit CMOS adders, circuits of which consist of 10 transistors. The comparison of main characteristics of adders has been carried out based on the results of circuit simulation for 0.18-micron MOS technology and the most promising implementations have been marked out.     

基于SD数表示的求和算法

二进制加法器已广泛应用于数字系统，但传统的二进制数表示求和过程中产生的进位限制了运算速度。文中提出了一种以2为基数的SD（Singed-Digit)数表示的求和计算方法，并在此基础上应用可编程逻辑器件设计实现了SD加法器，简化了求和运算过程。实验证明，通过这种算法可得到高速加法器，以提高运算速度。     

A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance

Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell contains a matrix of lookup tables that either implement mathematics functions or a random-access memory. A hierarchical interconnection network supports data transfer within and between modules. We have created software tools that allow users to map algorithms onto the reconfigurable platform. This paper analyzes the implementation of several common benchmarks, ranging from floating-point arithmetic to a radix-4 fast Fourier transform. The results are compared to contemporary DSP hardware.     

Single-electron devices and their applications

The goal of this paper is to review in brief the basic physics of single-election devices, as well as their-current and prospective applications. These devices based on the controllable transfer of single electrons between small conducting “islands”, have already enabled several important scientific experiments. Several other applications of analog single-election devices in unique scientific instrumentation and metrology seem quite feasible. On the other hand, the prospect of silicon transistors being replaced by single-electron devices in integrated digital circuits faces tough challenges and remains uncertain. Nevertheless, even if this replacement does not happen, single electronics will continue to play an important role by shedding light on the fundamental size limitations of new electronic devices. Moreover, recent research in this field has generated some by-product ideas which may revolutionize random-access-memory and digital-data-storage technologies     

Enhancing the super exponential method of blind equalisation withthe fast RLS Kalman algorithm

A method for efficiently implementing super exponential (SE) blind equalisation is proposed. The method, based on fast Kalman filtering theory, is recursive in order and in time, and leads to a significant reduction in the number of arithmetic operations. Using the order update by partitioning the covariance matrix of the first hundred data in a specific form, a fast initialisation is implemented. The resulting algorithm achieves the same theoretical fast convergence characteristics as the original SE algorithm but with a significant reduction in arithmetic operations     

Design and simulation of a nanoelectronic single electron 2-4 decoder using a novel simulator

The design and simulation of a single-electron 2-4 decoder using a novel single electron circuit simulation tool named single-electron circuit simulator (SECS), is presented in this paper. In single electron circuits bits of information are represented by the presence or absence of single electrons at conducting or semiconducting islands. SECS utilizes the Monte Carlo method and the change in free-energy of the whole circuit determines the tunnel rates of possible tunnel events, providing thus a real time simulation of any arbitrary single-electron circuit. Furthermore, SECS is using the SPICE interface for schematic capture. SPICE models of single-electron circuit structures have been developed and, therefore, SECS can also be used for the design and simulation of hybrid microelectronic—single-electron circuits.     

Dynamic-type CMOS four-valued logic circuits

We first briefly introduce the various kinds of basic CMOS four-valued logic circuit that can be suitably employed for circuits with clock pulses. Using these, the design of multiple-valued MAX and MIN circuits with many inputs, each of which has two quaternary figures, are developed. It is shown that the number of MOS transistors required for these circuits can be reduced in comparison to binary circuits having equivalent functions. Successful simulation results using SPICE-2 for the circuit operations are given.     

Complexity Reduction For FRM-based FIR Filters Using The Prefilter-Equalizer Technique

A new method to reduce the number of arithmetic operations in a sharp FIR filter synthesized by the frequency-response masking (FRM) technique is presented. The success of the proposed method is based on a modified FRM approach where the subfilters in the FRM approach are implemented by using recently introduced prefilter-equalizer based filters. It is shown, by means of examples, that the proposed method yields considerable savings in the numbers of multipliers and adders compared to the original single-stage FRM approach.     

基于RT器件的三值与非门、或非门电路设计

共振隧穿（resonant tunnel,RT）器件本身所具有的微分负阻（negative differential resistance,NDR）特性使其成为天然的多值器件，文中利用RT器件的负阻特性,以开关序列原理为指导,设计了基于RT电路的开关模型,实现了更为简单的三值RT与非门和或非门电路,并利用MOS网络模型,通过SPICE软件仿真验证了所设计电路的正确性，该设计思想可推广到更高值的多值电路设计中。     

Fast and gate-count efficient arithmetic logic unit

A CMOS arithmetic logic unit is presented with a minimum number of transistors and high speed arithmetic operations. Multiple carry chain adders and a novel 1 bit adder, are used in a carry select adder. The carry chain adder has a high degree of shared gates with a low propagation delay     

Robust HSPICE modeling of a single electron turnstile

This paper presents a novel HSPICE circuit model for designing and simulating a single-electron (SE) turnstile, as applicable at the nanometric feature sizes. The proposed SE model consists of two nearly similar parts whose operations are independent of each other; this disjoint feature permits the accurate and reliable modeling of the sequential transfer of electrons through the turnstile in the storage node (modeled on a voltage level basis). It therefore avoids the transient (current-based) nature of a previous model, thus ensuring robustness in simulated operation. The model has been simulated and results show that it can robustly operate at 32 and 45 nm with excellent stability in its operation. Extensive simulation results are presented to substantiate the advantages of using the proposed model with respect to changes in the circuit model parameters as related to capacitances, feature size and voltages.     

量子三值全加器设计

量子多值加法器是构建量子多值计算机的基本模块.通过认真分析三元域上加法的运算规则及带进位加法的真值表,通过设置扩展三值Toffoli门的控制条件有效实现一位加法在各种情况下的进位,利用三值Feynman门实现一位加法的求和运算,由此设计出一位量子三值全加器,再利用进位线将各位量子全加器连接起来构造出n位量子三值全加器.与同类电路相比,此量子全加器所使用的辅助线及量子代价都有所减少.     

Single-electron logic device based on the binary decision diagram

The unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for logic circuits of NAND, NOR, exclusive-OR, and AND-OR combinational logic. Computer simulation shows that the designed circuits perform the logic operations correctly     

基于开关信号理论的电流型CMOS多值施密特电路设计

以开关信号理论为指导,建立了描述电流型CMOS多值施密特电路中阈值控制电路的电流传输开关运算.在此基础上,提出了新的电流型CMOS三值和四值施密特触发器设计.所设计的电路可提供多值电流和电压输出信号,回差电流的大小只需通过改变MOS管的尺寸比来调节.所提出的电路较之以往设计具有结构简单,回差值调整容易以及可在较低电压下工作等特点.采用TSMC 0.25 μ m CMOS工艺参数和1.5V电压的HSPICE模拟结果验证了所提出设计方案的有效性和电路所具有的理想回差特性.