Defect structures in silicon merged epitaxial lateral overgrowth

Merging of two epitaxial lateral overgrowth fronts has been achieved to produce thin silicon-on-insulator (SOI) structures. The electronic quality of the material is generally of high quality; however, at the merger interface are defects associated with improper merging. Defects at the oxide/silicon interface and the merging interface were characterized using transmission electron microscopy. Device performance indicated the need for a process modification to improve the material quality for potential electronic applications.     

A new epitaxial lateral overgrowth silicon bipolar transistor

A new device structure and method of fabricating a silicon bipolar transistor is proposed. The device has reduced collector parasitic capacitance and resistance as compared to other advanced bipolar technologies. By using selective and lateral epitaxial overgrowth techniques the buried (N+) layer is not necessary. Two-dimensional computer simulations show theC_{CS} times R_{C}product to be reduced by a factor of 5.45 along with reduced CCB.     

Three dimensional devices fabricated by silicon epitaxial lateral overgrowth

Selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of silicon over oxide are used for novel device technologies in CMOS and bipolar with a large potential for BICMOS. A stacked inverted P-MOS device in crystalline Si on top of an oxidized poly-gate was fabricated with the critical “as-grown” interface state densities, between the ELO silicon grown over the existing poly-oxide, measured to be less than 2 × 10¹¹/ (cm²-eV) near midgap. A SiH₂Cl₂-HCl-H₂ in a LPCVD epitaxial system was employed at 150 Torr and at 900° C to produce the ELO/SEG material. The initial stacked-inverted 3D P-MOS devices typically show hole mobilities of greater than 160 cm²/V-s with adequate subthreshold characteristics for 3-dimensional CMOS implementation. A new form of SEG was used to grow single crystal silicon horizontally between dielectric walls to form SOI material in thin slabs, called confined lateral selective epitaxial growth (CLSEG). BJT-SOI device structures with β_dc > 150 were fabricated in CLSEG silicon to demonstrate the device quality material and to show the 3D-SOI capability.     

Lateral epitaxial overgrowth of silicon over recessed oxide

There has been considerable interest in silicon-on-insulator (SOI) technology recently because of its potential applications in VLSI. CMOS circuits in SOI have higher speed because of the absence of substrate capacitance, and freedom from latch-up because of dielectric isolation. Recently, memory circuits like DRAMs have reached the physical limits of what is possible in two dimensions, and hence there is a growing need for 3-dimensional circuits. SOI offers a possible avenue to realise such 3-D circuits and thus lead the way to the next generation of memories and integrated circuits.     

Confined lateral selective epitaxial growth of silicon for devicefabrication

An epitaxy technique, confined lateral selective epitaxial growth (CLSEG), which produces wide, thin slabs of single-crystal silicon over insulator, using only conventional processing, is discussed. As-grown films of CLSEG 0.9 μm thick, 8.0 μm wide, and 500 μm long were produced at 1000°C at reduced pressure. Junction diodes fabricated in CLSEG material show ideality factors of 1.05 with reverse leakage currents comparable to those of diodes built in SEG homoepitaxial material. Metal-gate p-channel MOSFETs in CLSEG with channel dopings of 2×10¹⁶ cm^-3 exhibit average mobilities of 283 cm²/V-s and subthreshold slopes of 223 mV/decade     

Atomic force microscopy studies of CdTe films grown by epitaxial lateral overgrowth

Epitaxial lateral overgrowth (ELO) of CdTe was carried out on GaAs using silicon nitride as the mask material. Windows were delineated on silicon, nitride mask deposited on GaAs substrates and CdTe was grown using metalorganic vapor phase epitaxy. The films were characterized by atomic force microscopy (AFM). It has been shown that highly selective growth of CdTe can be achieved at temperatures higher than 500 C and pressures lower than 25 torr using silicon nitride as the mask layer. Optimizing the growth conditions as well as the stripe directions on the substrates enables the growth of ELO-CdTe with a flattop surface and vertical sidewalls. AFM studies show that ELO-grown CdTe contains large grains with reduced defect densities, but there seems to be no difference on the films grown on the window region or on the masked region. The results suggest that the growth mechanism for CdTe growth on GaAs is different from that of ELO-grown GaN. A possible growth model for the patterned CdTe growth is also proposed.     

Square-extensional mode single-crystal silicon micromechanical resonator for low-phase-noise oscillator applications

A micromechanical 13.1-MHz bulk acoustic mode silicon resonator having a high quality factor (Q=130 000) and high maximum drive level (P= 0.12 mW at the hysteresis limit) is demonstrated. The prototype resonator is fabricated of single-crystal silicon by reactive ion etching of a silicon-on-insulator wafer. A demonstration oscillator based on the new resonator shows single-sideband phase noise of -138 dBc/Hz at 1 kHz offset from the carrier.     

Device characterization on monocrystalline silicon grown over SiO2by the ELO (epitaxial lateral overgrowth) process

MOS and lateral bipolar transistors have been fabricated on epitaxial silicon layers which have been laterally overgrown over SiO2. These device characteristics were than compared to those measured on devices fabricated on homoepitaxial silicon and bulk silicon. The measurements indicate essentially identical MOS device characteristics for all three materials with a typical hole field effect mobility of about 180 cm²/vs. Lifetime measurements using pulsed C-V techniques showed essentially the same values for ELO material and homoepitaxial material with the ELO value being about 20 µS for 10¹⁵cm^-3doping level. These lifetime values correlate will with diode and bipolar transistor measurements.     

一种新的深度传感器内部参数标定方法研究

针对双镜头深度传感器(以Kinect为例)出厂标 定参数精度不高的问题,提出一种新的标定方法。 对于Kinect 2.0深度镜头,利用空间线定长约束,通过间接平差方法求解待求参数;根据求 解参数,将深度图 像坐标转转换值Kinect坐标并将其与对应的彩色影像坐标点进行关联,基于中心投影方程标 定彩色镜头。实 验结果表明,本方法将深度影像点转换到Kinect坐标时精度优于2.5 mm,深度影像坐标转换至彩色影像坐标 时精度优于1pixel,高于Kinect微软开发包内置参数的计算精度,对一些需要较高参 数精度的应用,本文算法解算的参数更优。     

Surface characterization of epitaxial lateral overgrowth of InP on InP/GaAs substrate by MOCVD

Epitaxial lateral overgrowth (ELO) of InP on InP/GaAs substrates by low-pressure metalorganic chemical vapor deposition (LP-MOCVD) was investigated. The lateral overgrowth InP layers were obtained on the SiO₂ masked InP seed layer, which was deposited on the (1 0 0) GaAs substrate by the two-step method. The surface characterization of overgrowth InP was dependent on the V/III ratio, the mask width and the growth time. When decreasing the V/III ratio or reducing the mask width respectively, the sidewalls “competition effect” was obviously observed. After a longer time, new (1 0 0)-like top surfaces were formatted because of the precursors migrating from the sidewall facets to the (1 0 0) top surfaces. The experimental findings will be explained by growth kinetics in conjunction with the different dominant source supply mechanism.     

A new cell structure for very thin high-efficiency silicon solarcells

The cell has a corrugated structure, which is formed by aligned V grooves on both the front and back surfaces. The substrate thickness is reduced to 50 μm while retaining high mechanical strength. This permits ease of handling during the fabrication process and subsequent procedures. This thin substrate promises a very high open-circuit voltage, and the structure is also beneficial to high optical performance. The surface reflectance is reduced in the same manner as that of V-grooved cells, but the optical path is lengthened by a minimum of four times the substrate thickness. Performance of experimental cells is also discussed     

Scanning electron microscopy and cathodoluminescence study of the epitaxial lateral overgrowth (ELO) process for gallium nitride

Traditional epitaxial growth of GaN by metalorganic vapor phase epitaxy (MOVPE) on mismatched substrates such as sapphire or SiC produces a columnar material consisting of many hexagonal grains ∼0.2–1.0 μm in diameter. The epitaxial-lateral-overgrowth (ELO) process for GaN creates a new material: single-crystal GaN. We have studied the ELO process for GaN grown by MOVPE in a vertical flow rotating substrate reactor. Characterization consisted of plan-view SEM and vertical-cross-section TEM studies, which revealed a large reduction in dislocation density in the overgrown regions of the GaN. Panchromatic and monochromatic cathodoluminescence images and spectra were used to study the spatial variation of the optical properties within the GaN ELO samples. The effects of growth temperature and stripe material on the overgrown layers were examined. Through the use of a higher substrate temperature during growth and the use of a SiN_x stripe material, the overgrown crystal shape has a smooth 2D top surface with vertical sidewalls. Applying a second ELO step, rotated by 60°, over a fully coalesced ELO layer yields a further reduction of defects in GaN overgrown surfaces.     

A new method for distributing power usage across a sensor network

We present a method for more uniformly distributing the energy burden across a wireless ground-based sensor network communicating with an overhead unmanned aerial vehicle (UAV). A subset of sensor nodes, termed a transmit cluster, receives and aggregates data gathered by the entire network, and forms a distributed antenna array, concentrating the radiated transmission into a narrow beam aimed towards the UAV. Because these duties are power-intensive, the role of transmit cluster must be shifted to different nodes as time progresses. We present an algorithm to reassign the transmit cluster, specifying the time that should elapse between reassignments and the number of hops that should be placed between successive transmit clusters in order to achieve three competing goals: first, we wish to better and more broadly spread the energy load across the sensor network while, second, minimizing the energy expended in moving the transmit cluster, all the while, third, reducing to the extent practicable the time to bring the UAV and the sensor network’s beam into alignment. Additionally, we present a method for reconfiguring the communication burden between the ground-based sensor network and the UAV. We describe and analyze two alternative strategies to bring the UAV and the sensor network’s beam into alignment, while minimizing the energy expended by the sensor network. The performance of the two strategies is compared in terms of probability of beam-UAV alignment as a function of time, and the expected time to alignment. We examine the performance tradeoff between the choice of strategy and parameters of the sensor network that affect power conservation.     

A new DRAM cell with a transistor on a lateral epitaxial siliconlayer (TOLE cell)

A new dynamic RAM (DRAM) cell structure and its fabrication technology are proposed. The proposed DRAM cell consists of a transistor on a lateral epitaxial silicon layer (TOLE) and a stacked capacitor formed in a trench. It can achieve high immunity to alpha-particle-induced noise and a low parasitic bit-line capacitance. The TOLE structure is produced by a silicon-on-insulator fabrication technology newly developed by combining epitaxial lateral overgrowth and preferential polishing. Reasonable electrical characteristics for the TOLE and high immunity against alpha-particle disturbance for the TOLE cell were confirmed     

High‐rate deposition of epitaxial layers for efficient low‐temperature thin film epitaxial silicon solar cells

Low–temperature deposition of Si for thin‐film solar cells has previously been hampered by low deposition rates and low material quality, usually reflected by a low open‐circuit voltage of these solar cells. In contrast, ion‐assisted deposition produces Si films with a minority‐carrier diffusion length of 40 μm, obtained at a record deposition rate of 0.8 μm/min and a deposition temperature of 650°C with a prebake at 810°C. A thin‐film Si solar cell with a 20‐μm‐thick epitaxial layer achieves an open‐circuit voltage of 622 mV and a conversion efficiency of 12.7% without any light trapping structures and without high‐temperature solar cell process steps. Copyright © 2001 John Wiley & Sons, Ltd.     

Simulation and implementation of a porous silicon reflector for epitaxial silicon solar cells

One of the main challenges in the ongoing development of thin film crystalline silicon solar cells on a supporting silicon substrate is the implementation of a long‐wavelength reflector at the interface between the epitaxial layer and the substrate. IMEC has developed such a reflector based on electrochemical anodization of silicon to create a multi‐layer porous silicon stack with alternating high and low porosity layers. This innovation results in a 1–2% absolute increase in efficiency for screenprinted epitaxial cells with a record of 13·8%. To reach a better understanding of the reflector and to aid in its continued optimization, several extensive optical simulations have been performed using an in‐house‐developed optical software programme. This software is written as a Microsoft Excel workbook to make use of its user‐friendliness and modular structure. It can handle up to 15 individual dielectric layers and is used to determine the influence of the number and the sequence of the layers on the internal reflection. A sensitivity analysis is also presented. A study of the angle at which the light strikes the reflector shows separate regions in the physical working of the reflector which include a region where the Bragg effect is dominant as well as a region where total internal reflection plays the largest role. The existence of these regions is proved using reflection measurements. Based on these findings, an estimate is made for the achievable current gain with an ideal reflector and the potential of epitaxial silicon solar cells is determined. Copyright © 2008 John Wiley & Sons, Ltd.     

A new networking model for biological applications of ad hoc sensor networks

In this paper, we introduce the Shared Wireless Infostation Model (SWIM), which extends the Infostation model by incorporating information replication, storage, and diffusion into a mobile ad hoc network architecture with intermittent connectivity. SWIM is able to reduce the delay of packet delivery at the expense of increased storage at the network nodes. Furthermore, SWIM improves the overall capacity-delay tradeoff by only moderately increasing the storage requirements. This tradeoff is examined here in the context of a practical application-acquisition of telemetry data from radio-tagged whales. To reduce the storage requirements, without affecting the network delay, we propose and study a number of schemes for deletion of obsolete information from the network nodes. In particular, through the use of Markov chains, we compare the performance of five such storage deletion schemes, which, by increasing the computational complexity of the routing algorithm, mitigate the storage requirements. The results of our study will allow a network designer to implement such a system and to tune its performance in a delay-tolerant environment with intermittent connectivity, as to ensure with some chosen level of confidence that the information is successfully carried through the mobile network and delivered within some time period.     

Molecular-beam epitaxial growth of HgCdTe infrared focal-plane arrays on silicon substrates for midwave infrared applications

Molecular beam epitaxy has been employed to deposit HgCdTe infrared detector structures on Si(112) substrates with performance at 125K that is equivalent to detectors grown on conventional CdZnTe substrates. The detector structures are grown on Si via CdTe(112)B buffer layers, whose structural properties include x-ray rocking curve full width at half maximum of 63 arc-sec and near-surface etch pit density of 3–5 × 10⁵ cm⁻² for 9 μm thick CdTe films. HgCdTe p⁺-on-n device structures were grown by molecular beam epitaxy (MBE) on both bulk CdZnTe and Si with 125K cutoff wavelengths ranging from 3.5 to 5 μm. External quantum efficiencies of 70%, limited only by reflection loss at the uncoated Si-vacuum interface, were achieved for detectors on Si. The current-voltage (I-V) characteristics of MBE-grown detectors on CdZnTe and Si were found to be equivalent, with reverse breakdown voltages well in excess of 700 mV. The temperature dependences of the I-V characteristics of MBE-grown diodes on CdZnTe and Si were found to be essentially identical and in agreement with a diffusion-limited current model for temperatures down to 110K. The performance of MBE-grown diodes on Si is also equivalent to that of typical liquid phase epitaxy-grown devices on CdZnTe with R₀A products in the 10⁶–10⁷ Θ-cm² range for 3.6 μm cutoff at 125K and R₀A products in the 10⁴–10⁵ Θ-cm² range for 4.7 μm cutoff at 125K.     

A new 4H-SiC lateral merged double Schottky (LMDS) rectifier withexcellent forward and reverse characteristics

The novel characteristics of a new Schottky rectifier structure, known as the lateral merged double Schottky (LMDS) rectifier, on 4H-SiC are explored theoretically and compared with those of the compatible conventional 4H-SiC Schottky rectifiers. The anode of the proposed lateral device utilizes the trenches filled with a high barrier Schottky (HBS) metal to pinch off a low barrier Schottky (LBS) contact during reverse bids. Numerical simulation of any such SiC structure is complicated by the fact that the thermionic emission theory predicts the reverse leakage current to be orders of magnitude smaller than the measured data. We, therefore, first propose a simple empirical model for barrier height lowering to accurately estimate the reverse leakage current in a SiC Schottky contact. The accuracy of the empirical model is verified by comparing the simulated reverse leakage current with the reported experimental results on different SiC Schottky structures. Using the proposed empirical model, the two-dimensional (2-D) numerical simulations reveal that the new LMDS rectifier demonstrates about three orders of magnitude reduction in the reverse leakage current and two times higher reverse breakdown voltage when compared to the conventional lateral low barrier Schottky (LLBS) rectifier while keeping the forward voltage drop comparable to that of the conventional LLBS rectifier     

Interface characterization of silicon epitaxial lateral growth overexisting SiO2 for three-dimensional CMOS structures

The silicon-silicon dioxide interface created by the epitaxial lateral growth of monocrystalline silicon (ELO) over existing thermally oxidized silicon was investigated using a novel device structure. This structure is proposed as the basic building block of technology for the fabrication of locally restricted three-dimensional integrated CMOS circuits, as well as advanced bipolar devices. Results are reported from the investigation of the surface states of this silicon-on-insulator (SOI) interface. It is demonstrated that these interfaces can exhibit characteristics comparable to those interfaces created by the thermal oxidation of silicon. The SOI interface surface state densities, as grown, were measured to be about 2×10¹¹ cm^-2 eV^-1 at midgap energies. It is believed that H₂ from the epitaxial growth ambient is trapped at the interface and neutralizes surface states