Design of BLDCM Driving and Control System for Motorized Treadmill

To satisfy the requirement of developing a new generation of motorized treadmill for a famous domestic manufacturer, a brushless DC motor （BLDCM） driving and control system for motorized treadmill is developed. High integration and reliability of this system are ensured under the condition that intelligent power module （IPM） is used and the protection module is included. Periodic current control method is applied to reduce the average current flowing through the armature winding of the motor when the treadmill is required to start with low speed while large load is added. Piecewise proportion-integration-differentiation （PID） control algorithm is applied to solve the problem of speed fluctuation when impulse load is added. The motorized treadmill of a new generation with the driving and control system has the advantages of high reliability, good speed stability, wide timing scope, low cost, and long life-span. And it is very promising for practical applications.     

A novel high reliability CMOS SRAM cell

A novel 8T single-event-upset(SEU) hardened and high static noise margin(SNM) SRAM cell is proposed. By adding one transistor paralleled with each access transistor,the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell.So the hold,read SNM and critical charge increase greatly.The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors.The hold and read SNM of the new cell increase by 72%and 141.7%,respectively,compared to the 6T design,but it has a 54%area overhead and read performance penalty.According to these features,this novel cell suits high reliability applications,such as aerospace and military.     

Simulation study of new 3-terminal devices for high speed STT-RAM

To improve the performance of spin transfer torque random access memory(STT-RAM),especially writing speed,we propose three modified 3-terminal STT-RAM cells.A magnetic dynamic process in the new structures was investigated through micro-magnetic simulation.The best switching speed of the new structures is 120%faster than that of the rectangular 3-terminal device.The optimized 3-terminal device offers high speed while maintaining the high reliability of the 3-terminal structure.     

An ultra-low-power area-efficient non-volatile memory in a 0.18 μ m single-poly CMOS process for passive RFID tags

This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification(RFID) tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of (268 kb/s)/(3.0 kb/s).     

An Ultra-low-power Area-efficient Non-volatile Memory in 0.18μm Single-poly CMOS Process

This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 μm single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 μm single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 μm² and 0.12 mm², respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V. The power consumption of the read/write operation is 0.19 μW/0.69 μW at a read/write rate of (268 kb/s)/(3.0 kb/s).     

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells.If we want to reduce the overall power in the memory system,we have to work on the input circuitry of memory architecture i.e.row and column decoder.In this research work,low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed.In this work,the comparison of cluster DECODER,body bias DECODER,source bias DECODER,and source coupling DECODER are designed and analyzed for memory array application.Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool.Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92％ and static energy by 99.92％ at a supply voltage of 1.2 V.The proposed circuit also improves dynamic power dissipation by 5.69％,dynamic PDP/EDP 65.03％ and delay 57.25％ at 1.2 V supply voltage.     

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 ℃.     

Temperature-insensitive reading of a flash memory cell

The temperature characteristics of the read current of the NOR embedded flash memory with a 1.5T-per-cell structure are theoretically analyzed and experimentally verified. We verify that for a cell programmed with a “10” state, the read current is either increasing, decreasing, or invariable with the temperature, essentially depending on the reading overdrive voltage of the selected bitcell, or its programming strength. By precisely controlling the programming strength and thus manipulating its ...     

A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation

This paper presents a new dual Vt 8T SRAM cell having single bit-line read and write,in addition to Write Assist and Read Isolation (WARI).Also a faster write back scheme is proposed for the half selected cells.A high Vt device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write.The proposed cell provides an improved read static noise margin (RSNM) due to the bit-line isolation during the read.Static noise margins for data read (RSNM),write (WSNM),read delay,write delay,data retention voltage (DRV),leakage and average powers have been calculated.The proposed cell was found to operate properly at a supply voltage as small as 0.41 V.A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay,pulse timing hardware requirements and power consumption.The proposed new WARI 8T cell shows better performance in terms of easier write,improved read noise margin,reduced leakage power,and less delay as compared to the existing schemes that have been available so far.It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.     

A low standby-power fast carbon nanotube ternary SRAM cell with improved stability

Power dissipation,speed and stability are the most important parameters for multiple-valued SRAM design.To reduce the power consumption and further improve the performance of the ternary SRAM cell,we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors (CNFETs).The performance is simulated in terms of three criteria including standby-power,delay (write and read) and stability (RSNM).Compared to the novel ternary SRAM cell,our results show that the average standby-power,write and read delay of the proposed cell are reduced by 78.1％,39.6％ and 58.2％,respectively.In addition,the RSNM under process variations is 2.01 × and 1.95× of the conventional and novel ternary SRAM cells,respectively.     

A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function

This paper describes a 1.8-V-only 256-Mb four-level-cell (2 b/cell) NOR flash memory with background operation (BGO) function fabricated in a 130-nm CMOS self-aligned shallow trench isolation (SA-STI) process technology. The new memory array architecture is adopted in which the flash source is connected by local interconnect to reduce the source resistance and constrain the floating-gate coupling effect. The mirrored current sensing read architecture for multilevel-cell operation at a supply voltage of 1.8 V has realized a fast asynchronous random access time (67 ns) and burst read at 54 MHz. A high speed and high reliability of program/erase cycling (100 k) has been achieved by dual-step pulse program algorithm and optimized erase sequence. Page program time and block erase time are 1.54 ms/2 kb and 538 ms/1 Mb, respectively     

Printed Organic One‐Time Programmable ROM Array Using Anti‐fuse Capacitor

This paper proposes printed organic one‐time programmable read‐only memory (PROM). The organic PROM cell consists of a capacitor and an organic p‐type metal‐oxide semiconductor (PMOS) transistor. Initially, all organic PROM cells with unbroken capacitors store “0.” Some organic PROM cells are programmed to “1” by electrically breaking each capacitor with a high voltage. After the capacitor breaking, the current flowing through the PROM cell significantly increases. The memory data is read out by sensing the current in the PROM cell. 16‐bit organic PROM cell arrays are fabricated with the printed organic PMOS transistor and capacitor process. The organic PROM cells are programmed with –50 V, and they are read out with –20 V. The area of the 16‐bit organic PROM array is 70.6 mm².     

一种采用带-带隧穿热电子注入编程的新型快闪存贮器

提出一种采用带-带隧穿热电子注入编程的新型快闪存贮器结构,在便携式低功耗的code闪存中有着广泛的应用前景.该结构采用带-带隧穿热电子注入 (BBHE)进行"写"编程,采用源极Fowler-Nordheim隧穿机制进行擦除.研究显示控制栅编程电压为8V,漏极漏电流只有3μA/μm左右,注入系数为4×10-4,编程速度可达16μs,0.8μm存贮管的读电流可达60μA/μm.该新型结构具有高编程速度、低编程电压、低功耗、大读电流和高访问速度等优点.     

Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations

The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations.     

一种采用带-带隧穿热电子注入编程的新型快闪存贮器

提出一种采用带-带隧穿热电子注入编程的新型快闪存贮器结构,在便携式低功耗的code闪存中有着广泛的应用前景.该结构采用带-带隧穿热电子注入 (BBHE)进行"写"编程,采用源极Fowler-Nordheim隧穿机制进行擦除.研究显示控制栅编程电压为8V,漏极漏电流只有3μA/μm左右,注入系数为4×10-4,编程速度可达16μs,0.8μm存贮管的读电流可达60μA/μm.该新型结构具有高编程速度、低编程电压、低功耗、大读电流和高访问速度等优点.     

A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology

Shrinking of technology node in advanced VLSI devices and scaling of supply voltage degrade the performance characteristics and reduce the soft error resilience of modern downscaled digital circuits. In this paper, we propose a reliable near-threshold 7T SRAM cell with single ended read and differential write operations based on a previous proposed 5T cell. Our new cell improves read speed without degrading of write speed compared to the recently reported 7T cell. Furthermore, our proposed cell provides high soft error reliability amongst all the SRAM cells mentioned in this paper. We compared the performance and reliability characteristics of 5T, 6T, 8T and previous 7T cells with our new 7T SRAM cell to show its efficacy. The simulations are performed using HSPICE in 20 nm FinFET technology at V_DD = 0.5 V. The results show that the new 7T cell has high write speed, read and write margins with improved read speed and low leakage power in the hold “0” state compared to 5T cell. In addition, the study of performance parameters under process and environmental variations considering ageing effect in near-threshold region shows the robustness of the proposed 7T SRAM cell against these variations.     

Polymer composite of poly(vinyl phenol)-reduced graphene oxide reduced by vitamin C in low energy consuming write-once–read-many times memory devices

We report the application of reduced graphene oxide, using vitamin C as reducing agent, to make a composite with poly(vinyl phenol) as the active layer of write-once–read-many times memory devices. These devices present a high ON/OFF current ratio of 10⁵ when read at 1 V, retain the information for a long time maintaining the ON/OFF current ratio constant, and require low energy for performing at 5 V the memory write (less than 10^?8 J cm^?2 device active area) and read operations.     

Highly scalable ballistic injection AND-type (BiAND) flash memory

An AND-type split-gate Flash memory cell with a trench select gate and a buried n/sup +/ source is proposed. This cell, programmed by ballistic source side injection (BSSI), can provide high programming efficiency with a cell size of 5F/sup 2/. Furthermore, both the programming speed and the read current are enhanced by the shared select gate configuration.     

基于SiGe量子点实现增强F-N隧穿的低压闪速存储器

提出了一种用于半导体闪速存储器单元的新的Si/SiGe量子点/隧穿氧化层/多晶硅栅多层结构,该结构可以实现增强F-N隧穿的编程和擦除机制.模拟结果表明该结构具有高速和高可靠性的优点.测试结果表明该结构的工作电压比传统NAND结构的存储器单元降低了4V.采用该结构能够实现高速、低功耗和高可靠性的半导体闪速存储器.     

Bi-stable switching behaviors of ITO/EVA:ZnO NPs/ITO transparent memory devices fabricated using a thermal roll lamination technique

This research reported the transparent non-volatile write-once-read-many-times (WORM) memory behaviors of memory devices based on zinc oxide nanoparticles (ZnO NPs) embedded in an insulating poly(ethylene-co-vinyl acetate) (EVA), sandwiched between two ITO-coated flexible polyethylene naphthalate (PEN) substrates. The memory devices were fabricated employing a thermal roll lamination technique with the laminated-structure of PEN/ITO/EVA:ZnO NPs/ITO/PEN. The average transmittance of the laminated memory device was over 70% for an optical visible range of 400–800 nm. The maximum ON/OFF current ratio for the memory device was about 10³. In addition, a reliability study for continuous read operations in a long time memory device is presented. The conductance switching mechanisms of the laminated memory device were analyzed using theoretical models on the basis of the experimental data.