Design of high speed LVDS transceiver ICs

The design of low-power LVDS(low voltage differential signaling) transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/s.For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers.In addition,the LVDS receiver also supports ...     

一个0.18μm高速低功耗的发送和接收电路

提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它町以工作到1.6Gb/s.芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s,同时发送和接收端的功耗分别是35和6mW.     

一个0.18μm高速低功耗的发送和接收电路

提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它町以工作到1.6Gb/s.芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s,同时发送和接收端的功耗分别是35和6mW.     

一种6.25 Gb/s带预加重结构的低压差分发送器

采用SMIC 40 nm CMOS工艺,设计了一种带预加重结构的低压差分(LVDS)发送器。低压差分驱动器采用双运放反馈控制电路,可稳定输出信号的摆幅。采用边沿检测电流注入的预加重电路,对输出进行高频预加重,克服了数据高速传输中高频信号的损失。该发送器的速率为6.25 Gb/s,输出差分信号摆幅为300 mV,预加重比例为3.5 dB,功耗为7.1 mW。该低压差分发送器可应用于高速IO物理层电路中。     

一种基于CMOS工艺的Gbps高速LVDS发送电路

低压差分信号（LVDS）是用于高速低功耗数据传输的一种非常理想的传输技术。由于使用全差分技术和低电压摆幅,LVDS技术达到高速度的同时消耗的功耗非常小。设计了一种具有Gbps发送速度的LVDS发送电路。通过在输出采用闭环控制模式,使得LVDS输出共模电平和电压幅值被控制在一个合理的范围内。基于SMIC 0．18μm CMOS工艺模型,采用Hspice仿真器对整个发送电路进行模拟,结果表明所设计的发送电路具有4Gbps发送速度,功耗仅为18．6mW。     

千兆比特数据率LVDS接口电路设计

设计了一个采用0.18μm1.8V/3.3V CMOS工艺制造的千兆比特数据率LVDS I/O接口电路。发送器电路采用内部参考电流源和片上匹配电阻,使工艺偏差、温度变化对输出信号幅度的影响减小50%;接收器电路采用一种改进的结构,通过检测输入共模电平,自适应调整预放大器偏置电压,保证跨导Gm在LVDS标准[1]要求的共模范围内恒定,因此芯片在接收端引入的抖动最小。芯片面积0.175mm2,3.3V电源电压下功耗为33mW,测试表明此接口传输速率达到1Gb/s。     

A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination

In this work, a novel circuit topology for a Low-Voltage Differential Signaling (LVDS) output driver with reduced power consumption is proposed. Also, a low-signal current version of the LVDS driver working with lower supply voltage is proposed along with a compatible differential current-mode receiver. Both the drivers and the receiver feature active-terminated ports that eliminate the need for a dedicated passive terminator for matching. An asymmetric impedance network on the output side of the driver selectively eliminates any reflections coming from the channel while providing a high output impedance to the outgoing signal. For a target signal swing at the receiver input, the proposed termination scheme helps to reduce the driver signal current to up to a third of the current required by a conventional LVDS driver using a passive termination at the output. The asymmetric impedance network consists of a scaled-down replica driver that drives a common drain stage acting as the load for the main driver. The proposed driver topology meeting all LVDS specifications has been implemented in 3.3-V thick-gate CMOS technology. Simulation results show an achievable data rate of 5 Gb/s while transmitting over a 7.5-in FR4 PCB backplane trace for a target BER of 10⁻¹⁵, with power consumption equal to 17.8 mW, which is 25% less than a conventional LVDS driver with passive source end termination producing the same voltage swing at the receiver input. The low-current version of the driver has been implemented in 0.18-μm 1.8-V digital CMOS technology and shows similar performance over the same channel with a power consumption of 4.5 mW.     

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross‐coupled low‐voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross‐coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak‐to‐peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.     

Equalization and pre-emphasis based LVDS transceiver

This work presents an area-efficient, low-power, high data rate low voltage differential signal (LVDS) transmitter and receiver with signal quality enhancing techniques. The proposed common mode feedback scheme significantly reduces the size of the LVDS transmitter by eliminating the use of area consuming passive resistor and capacitor used for close loop stability compensation. A preemphasis technique has been introduced to enhance the transmitter output’s signal quality without significantly increasing the power draw. On the receiver part, an equalization technique has also been introduced to further enhance signal quality, increases data rate and improved jitter with relatively low power consumption. The LVDS transmitter consumes 5.4 mA of current while driving an external 100 ohm resistor with an output voltage swing of 440 mV. The chip consumes an area of 0.044 mm². This LVDS receiver has an input common mode range from 0.1 to 1.6 V. It consumes 34 mW of power with a maximum data rate of 2 Gbps. It consumes an area of 0.147 mm² a jitter of 11.74 ps rms. A test chip is implemented using 0.18 μm CMOS process.     

Low-power LVDS I/O interface for above 2Gb/s-per-pin operation

Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable ...     

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS

This paper presents the first fully integrated SONET OC-192 transmitter and receiver fabricated in a standard 0.18-/spl mu/m CMOS process. The transmitter consists of an input data register, 16-b-wide first-in-first-out (FIFO) circuit, clock multiplier unit (CMU), and 16:1 multiplexer to give a 10-Gb/s serial output. The receiver integrates an input amplifier for 10-Gb/s data, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. An on-chip LC-type voltage-controlled oscillator (VCO) is employed by both the transmitter and receiver. The chipset operates at multiple data rates (9.95-10.71 Gb/s) with functionality compatible with the multisource agreement (MSA) for 10-Gb transponders. Both chips demonstrate SONET-compliant jitter characteristics. The transmitter 10.66-GHz output clock jitter is 0.065 UI/sub pp/ (unit interval, peak-to-peak) over a 50-kHz-80-MHz bandwidth. The receiver jitter tolerance is more than 0.4 UI/sub pp/ at high frequencies (4-80 MHz). A high level of integration and low-power consumption is achieved by using a standard CMOS process. The transmitter and receiver dissipate a total power of 1.32 W at 1.8 V and are packaged in a plastic ball grid array with a footprint of 11/spl times/11 mm/sup 2/.     

一种应用于8B/10B编码串并转换电路的低功耗LVDS接收器设计

低电压差分信号(LVDS)是串并转换电路(SerDes)的一种主流接口技术.本文设计并实现了一种适合于8B/10B编码串并转换电路的LVDS接收器(Receiver).本设计的指标完全兼容IEEEStd1593.3-1996标准.它支持最大0.05 V至2.35 V的共模电平输入范围,最小100 mV的差模输入,能够在至少40英寸FR4带状线上达到1.6 Gb/s的接收速率,平均功耗3 mw.电路设计基于0.18μm1.8 V/*3.3 VCMOS工艺,同时采用了3.3 V器件和1.8 V器件.     

一种新型的低电磁干扰的亚低压差分接收器

本文介绍了一种低电磁干扰的用于标准移动图像架构的亚低压差分（subLVDS）接收器，它符合标准移动图像架构（SMIA）标准。由于使用了差分结构和小摆幅信号，它可以同时实现低功耗和高速传输。在本文描述的接收器电路里，高速的共模范围变化的小幅度信号成功的被接收和恢复。本电路在中芯国际1．2V／2．5V1p5m0．13μm CMOS逻辑工艺上投片，伪随机码传输高达1．4Gbps。     

一种低功耗的高速光接收器跨阻前置电路设计

为了降低芯片面积和功耗,提出了一种10 Gb/s光接收器跨阻前置放大电路。该电路采用了两个带有可调共源共栅（RGC）输入的交叉有源反馈结构,其中的跨阻放大器未使用电感,从而减少了芯片的总体尺寸。该跨阻前置电路采用0.13μm CMOS工艺设计而成,数据速率高达10 Gb/s。测试结果表明,相比其他类似电路,提出的电路芯片面积和功耗更小,芯片面积仅为0.072mm2,当电源电压为1.3 V时,功率损耗为9.1 mW,实测平均等效输入噪声电流谱密度为20pA/（0.1-10）Hz,且-3dB带宽为6.9 GHz。     

Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS

This paper presents high-speed differential input and output (I/O) interface circuits for gigabit-per-second serial data communication. The circuits are implemented in a 3.3-V/0.35-μm CMOS process. Signal levels are compatible with industry standards for low-voltage positive emitter-coupled logic (ECL), with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pullups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. Combining circuit techniques with the features of a submicrometer technology, the presented I/O blocks enable a full-CMOS chip to communicate with high-speed ECL-compatible systems and ease up a common I/O-related speed bottleneck. The circuits operate at 622 Mb/s (OC-12) and 1.24 Gb/s (OC-24) in a repeater and a retimer configuration. The asynchronous performance of the receiver and the transmitter was tested at rates up to 2.5 Gb/s     

High-gain transimpedance amplifier in InP-based HBT technology forthe receiver in 40-Gb/s optical-fiber TDM links

A monolithic integrated transimpedance amplifier for the receiver in a 40-Gb/s optical-fiber TDM system has been fabricated in an InP-based HBT technology. Despite its high gain (transimpedance of 2 kΩ in the limiting mode, 10 kΩ in the linear mode) the complete amplifier was realized on a single chip. Clear output eye diagrams were measured up to 43 Gb/s under realistic driving conditions. The voltage swing of 0.6 V_pp at the differential 50 Ω output does not change within the demanded input dynamic range of 6 dB. At the upper input current level even 48 Gb/s were achieved. The power consumption is approximately 600 mW at a single supply voltage of -5.5 V     

Design and realization of 1.3?Gb/s off-chip transmission circuitry using 0.35?μm CMOS technology

Low-voltage-differential-signaling (LVDS) is one of the very popular technologies which simultaneously addresses low dynamic power consumption and high data rate transmission in modern high speed circuit applications. In this paper, system level integration design approach is applied to design LVDS transmitter featuring high off-chip data rate. Full wave electromagnetic simulation technique was adopted to accurately characterize possible couplings and parasitic effects induced from the off-chip components which then acted as the termination of the output circuitry. Common mode feedback was included to perform fine tuning on the offset leading to much higher overall precision. Meanwhile, generation of the controlled current and voltage across termination was guaranteed through the introduction of a constant transconductance bias network. The design was implemented using TSMC 3.3?V 0.35???m CMOS technology with overall chip size of 0.923?mm². At a DC power consumption level of 29.4?mW, the LVDS transmitter exhibited an off-chip data rate of 1.3?Gb/s validated through measurements.     

Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS

Low-power building blocks for a serial transmitter operating up to 86 Gb/s are designed and implemented in a 130-nm SiGe BiCMOS technology with 150-GHz SiGe f_T HBT. Design techniques are presented which aim to minimize high-speed building block power consumption. They include lowering the supply voltage by employing a true BiCMOS high-speed logic family, as well as reducing current consumption by trading off tail currents for inductive peaking. A serial transmitter testchip consuming under 1 W is fabricated and operation is verified up to 86 Gb/s at room temperature (92 Gb/s and 71 Gb/s at 0degC and 100degC, respectively). The circuit operates from a 2.5-V supply voltage, which is the lowest supply voltage for circuits at this data rate in silicon technologies reported to date.     

A 20-Gb/s CMOS multichannel transmitter and receiver chip set forultra-high-resolution digital displays

A multichannel transmitter (TX) and receiver (RX) chip set operating at 20 Gb/s (5 Gb/s×4 ch) has been developed by using 0.25-μm CMOS technology. To achieve multichannel data transmission and high-speed operation, the chip set features: (1) circuits for compensating the phase difference between multiple RX chips, which is due to data skew resulting from different lengths of transmission cables, and for compensating the frequency difference between the system clocks of the TX and RX chips; (2) a self-alignment phase detector with parallel output for a high-speed data-recovery circuit; and (3) a fully pipelined 8B10B encoder. At a 2.5-V power supply, the power consumption of the TX chip during 5-Gb/s operation is 500 mW and that of the RX chip is 750 mW. Four of these TX/RX chip sets can provide an aggregate bandwidth of 20 Gb/s