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1.
    
We revisit robust complex‐ and mixed‐ µ‐synthesis problems based on upper bounds and show that they can be recast as specially structured controller design programs. The proposed reformulations suggest a streamlined handling of µ‐synthesis problems using recently developed (local) nonsmooth optimization methods, where both scalings or multipliers and a controller of given structure are obtained simultaneously. A first cut of the nonsmooth programming software for structured H∞ synthesis is made available through the MATLAB R2010b Prerelease, Robust Control Toolbox Version 3.5 developed by The MathWorks, Inc. Copyright © 2010 John Wiley & Sons, Ltd.  相似文献   

2.
    
In high‐speed network monitoring, the ever‐growing traffic calls for a high‐performance solution for the computation of frequent items. The increasing number of cores in the current commodity multi‐core processors opens up new opportunities in parallelization. In this paper, we present a novel precision integrated framework (PRIF) that exploits the great parallel capability of multi‐cores to speed up the famous frequent algorithm. PRIF equally distributes the input data stream into sub‐threads that use the optimized weighted frequent algorithm to track local frequent items. The items with frequency increments exceeding a pre‐defined threshold are sent to a merging thread which is able to return the global continuous ε‐deficient frequent items. The theoretical correctness and complexity analyses are presented. Experiments with real and synthetic traces confirm the theoretical analyses and demonstrate the excellent performance as well as the effects of parameters and data skewness. The results show that PRIF is able to provide continuous frequent items and near‐linear speedup at the cost of greater memory use. Copyright © 2013 John Wiley & Sons, Ltd.  相似文献   

3.
    
Exploitation of the NP hard, mixed µ problem structure provides a polynomial time algorithm that approximates µ with usually reasonable answers. When the problem is extended to the skew µ problem an extension of the existing method to the skew µ formulation is required. The focus of this paper is to extend the µ lower bound derivation to the skew µ lower bound and show its direct computation by way of a power algorithm. Copyright © 2005 John Wiley & Sons, Ltd.  相似文献   

4.
    
The promise of future many‐core processors, with hundreds of threads running concurrently, has led the developers of linear algebra libraries to rethink their design in order to extract more parallelism, further exploit data locality, attain better load balance, and pay careful attention to the critical path of computation. In this paper we describe how existing serial libraries such as (C)LAPACK and FLAME can be easily parallelized using the SMPSs tools, consisting of a few OpenMP‐like pragmas and a run‐time system. In the LAPACK case, this usually requires the development of blocked algorithms for simple BLAS‐level operations, which expose concurrency at a finer grain. For better performance, our experimental results indicate that column‐major order, as employed by this library, needs to be abandoned in benefit of a block data layout. This will require a deeper rewrite of LAPACK or, alternatively, a dynamic conversion of the storage pattern at run‐time. The parallelization of FLAME routines using SMPSs is simpler as this library includes blocked algorithms (or algorithms‐by‐blocks in the FLAME argot) for most operations and storage‐by‐blocks (or block data layout) is already in place. Copyright © 2009 John Wiley & Sons, Ltd.  相似文献   

5.
    
This paper considers the application of the skewed structured singular value to the robust stability of systems subject to strictly real parametric uncertainty. Three state‐space formulations that counteract the discontinuous nature of this problem are detailed. It is shown that the calculation of the supremum of the structured singular value over a frequency range using these formulations transforms into a single skewed structured singular value calculation. Similar to the structured singular value, the exact calculation of the skewed structured singular value is an NP‐hard problem. In this work, two efficient algorithms that determine upper and lower bounds on the skewed structured singular value are presented. These algorithms are critically assessed using a series of robustness analysis tests on a safety‐critical experimental drive‐by‐wire vehicle. Copyright © 2008 John Wiley & Sons, Ltd.  相似文献   

6.
    
Finding the longest common subsequence between two strings in acceptable time frames is crucial to solving various problems in different fields of study. To ensure the optimal solution is found, algorithms based on dynamic programming are employed almost exclusively. While the most commonly adopted algorithm, proposed by Needleman and Wunsch, has quadratic time and space complexity, the linear space complexity of Hirschberg's algorithm favors the comparisons of longer sequences. However, it too has a quadratic time complexity and therefore the effective exploitation of parallelism has become essential. This paper focuses on improving the execution efficiency of Hirschberg's algorithm on multi‐core and many‐core systems. To achieve this goal, first, enhancements to the sequential version are proposed to take advantage of SIMD instructions available on modern processors. Second, the impact on the performance of different parallelization strategies is investigated and evaluated. Results show that combining these two aspects can greatly improve the performance of Hirschberg's algorithm on these architectures. In relation to the original version, speedups of over 46 were achieved on a dual 18‐core server for sequences of 1.6 million characters. Furthermore, experiments with a 68‐core Intel Xeon Phi (many‐core) system obtained speedups of up to 105 for the same sequence size.  相似文献   

7.
Networks of transputers are often used for array processing applications. Programming such systems in OCCAM can be tedious and error-prone. This paper outlines a language designed to facilitate the solution of problems which involve some array processing. The language is called LATIN, and is currently being implemented on a transputer network. An example of its use is given.  相似文献   

8.
    
This article reports the simulated performance of rectangular coaxial ferrite phase shifter at Ka‐band. The proposed technique exploits rectangular coaxial waveguide with a symmetrically placed inner signal conductor inside an outer conductor connected to the ground. Strontium ferrite‐SU8 composite is used as an anisotropic material of choice in the modeled design. Two model phase shifting structures were designed for reciprocal and nonreciprocal applications using High Frequency Structure Simulator, HFSS. The reciprocal model produced a tunable phase shift of almost across 0 to 400 kA/m applied field and at 1800 Gauss. The predicted simulated performance of the nonreciprocal phase shifter was from a reference phase of at 0 A/m at the same saturation magnetization. A return loss better than 20 dB and an insertion loss less than 1.5 dB were predicted for the two models. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:502–509, 2015.  相似文献   

9.
    
A conceptually different approach to the µ‐synthesis robust performance problem is proposed in this article. The optimization problem posed maximizes the performance weights with respect to a suitable cost function that captures the desired closed‐loop performance. This maximization of performance weights is limited by the fact that there must exist some internally stabilizing controller that guarantees robust performance with respect to these maximized weights. Thus, performance weights and a controller that achieves an optimized level of robust performance are synthesized together by one algorithm in a systematic way. The designer is only required to specify the plant set and an optimization directionality. This directionality only appears in the cost function and reflects the desired closed‐loop properties in particular frequency regions. It is pointed out that choosing this directionality is much easier than choosing the performance weights directly. Correspondingly, this approach greatly simplifies the often long and tedious process of designing ‘good’ performance weights directly and gives an indication of what is the achievable performance. A pointwise in frequency solution to the posed optimization problem is also developed in this article. Copyright © 2005 John Wiley & Sons, Ltd.  相似文献   

10.
    
In this paper, the problem of attitude control of a three dimension nonlinear flexible spacecraft is investigated. Two nonlinear controllers are presented. The first controller is based on dynamic inversion, while the second approach is composed of dynamic inversion and µ‐synthesis schemes. It is assumed that only three torques in three directions on the hub are used. Actuator saturation is also considered in the design of controllers. To evaluate the performance of the proposed controllers, an extensive number of simulations on a nonlinear model of the spacecraft are performed. The performances of the proposed controllers are compared in terms of nominal performance, robustness to uncertainties, vibration suppression of panel, sensitivity to measurement noise, environmental disturbance and nonlinearity in large maneuvers. Simulation results confirm the ability of the proposed controller in tracking the attitude trajectory while suppressing the panel vibration. It is also verified that the perturbations, environment disturbances and measurement errors have only slight effects on the tracking and suppression performances. Copyright © 2010 John Wiley and Sons Asia Pte Ltd and Chinese Automatic Control Society  相似文献   

11.
    
We present a non‐trivial case study designed to highlight some of the practical issues that arise when using mixed‐µ or complex‐µ robust synthesis methodologies. By considering a multi‐input multi‐output three‐cart mass–spring–dashpot (MSD) with uncertain parameters and dynamics, it is demonstrated that optimized performance (disturbance‐rejection) is reduced as the level of uncertainty in one or two real parameters is increased. Comparisons are made (a) in the frequency domain, (b) by RMS values of key signals and (c) in time‐domain simulations. The mixed‐µ controllers designed are shown to yield superior performance as compared with the classical complex‐µ design. The singular value decomposition analysis shows the directionality changes resulting from different uncertainty levels and from the use of different frequency weights. The nominal and marginal stability regions of the closed‐loop system are studied and discussed, illustrating how stability margins can be extended at the cost of reducing performance. Copyright © 2008 John Wiley & Sons, Ltd.  相似文献   

12.
    
An optimized parallel algorithm is proposed to solve the problem occurred in the process of complicated backward substitution of cyclic reduction during solving tridiagonal linear systems. Adopting a hybrid parallel model, this algorithm combines the cyclic reduction method and the partition method. This hybrid algorithm has simple backward substitution on parallel computers comparing with the cyclic reduction method. In this paper, the operation count and execution time are obtained to evaluate and make comparison for these methods. On the basis of results of these measured parameters, the hybrid algorithm using the hybrid approach with a multi‐threading implementation achieves better efficiency than the other parallel methods, that is, the cyclic reduction and the partition methods. In particular, the approach involved in this paper has the least scalar operation count and the shortest execution time on a multi‐core computer when the size of equations meets some dimension threshold. The hybrid parallel algorithm improves the performance of the cyclic reduction and partition methods by 19.2% and 13.2%, respectively. In addition, by comparing the single‐iteration and multi‐iteration hybrid parallel algorithms, it is found that increasing iteration steps of the cyclic reduction method does not affect the performance of the hybrid parallel algorithm very much. Copyright © 2015 John Wiley & Sons, Ltd.  相似文献   

13.
    
This paper describes the design and implementation of an Efficient Architecture for Running THreads (EARTH) runtime system for a multi‐processor/multi‐node cluster. The (EARTH) model was designed to support the efficient execution of parallel (multi‐threaded) programs with irregular fine‐grain parallelism using off‐the‐shelf computers. Implementing an EARTH runtime system requires an explicitly threaded runtime system. For portability, we built this runtime system on top of Pthreads under Linux and used sockets for inter‐node communication. Moreover, in order to make the best use of the resources available on a cluster of symmetric multi‐processors (SMP), this implementation enables the overlapping of communication and computation. We used Threaded‐C, a language designed to implement the programming model supported by the EARTH architecture. This language allows the expression of various levels of parallelism and provides the primitives needed to manage the required communication and synchronization. The Threaded‐C programming language supports irregular fine‐grain parallelism through a two‐level hierarchy of threads and fibers. It also provides various synchronization and communication constructs that reflect the nature of EARTH's fibers—non‐preemptive execution with data‐driven scheduling—as well as the extensive use of split‐phase transactions on EARTH to execute long‐latency operations. Copyright © 2003 John Wiley & Sons, Ltd.  相似文献   

14.
    
This paper introduces hybrid address spaces as a fundamental design methodology for implementing scalable runtime systems on many-core architectures without hardware support for cache coherence. We use hybrid address spaces for an implementation of MapReduce, a programming model for large-scale data processing, and the implementation of a remote memory access (RMA) model. Both implementations are available on the Intel SCC and are portable to similar architectures. We present the design and implementation of HyMR, a MapReduce runtime system whereby different stages and the synchronization operations between them alternate between a distributed memory address space and a shared memory address space, to improve performance and scalability. We compare HyMR to a reference implementation and we find that HyMR improves performance by a factor of 1.71× over a set of representative MapReduce benchmarks. We also compare HyMR with Phoenix++, a state-of-art implementation for systems with hardware-managed cache coherence in terms of scalability and sustained to peak data processing bandwidth, where HyMR demonstrates improvements of a factor of 3.1× and 3.2× respectively. We further evaluate our hybrid remote memory access (HyRMA) programming model and assess its performance to be superior of that of message passing.  相似文献   

15.
    
A dual‐band eight‐antenna array operating in the long‐term evolution (LTE) band 41 (2.496‐2.69 GHz) and 3.5‐GHz band (3.3‐3.7 GHz) for fifth‐generation (5G) metal‐framed smartphone is presented. The proposed dual‐band antenna array is composed of four identical dual‐antenna building blocks (DABBs). Each DABB consists of two identical antenna elements with a neutralization line between them. The antenna array is simulated, fabricated, and measured. The isolations are better than 10.5 dB and 11.0 dB in the low band (LB; LTE band 41) and high band (HB; 3.5‐GHz band). The total efficiencies are 41% to 54% and 46% to 64% in the two operation bands, respectively. In addition, the measured envelope correlation coefficients are less than 0.11 and 0.06, the calculated channel capacities are better than 34.5 and 36.3 bps/Hz in the LB and HB, respectively. Furthermore, four hand‐grip scenarios are investigated, and results show that proposed antenna array can maintain excellent multiple‐input multiple‐output performances in all scenarios.  相似文献   

16.
由于当前硬件的开发逐日增加,为了充分发挥这些硬件的功能,通过介绍数据流编程语言的应用方式,一同介绍了数据流语言所充分利用的类似流程图的用法.利用智能编译器进行检测程序过程,陈述了与硬件地址相结合的编程方法.这种方法极大地简化了开发人员编写多线程程序的难处,同时能够充分发挥多棱CPU的效率.  相似文献   

17.
    
Memory access scheduling is an effective manner to improve performance of Chip Multi-Processors (CMPs) by taking advantage of the timing characteristics of a DRAM. A memory access scheduler can subdivide resources utilization (banks and rows) to increase throughput by accessing different DRAM banks in parallel. However, different threads running on different cores may exhibit different performance. One thread may experience starvation while the others are serviced normally. Therefore, designing a scheduler which reduces the unfairness in the DRAM system, while also improving system throughput on a variety of workloads and systems, is necessary. In this paper, a distributed fair DRAM scheduling for two-dimensional mesh network-on-chips (NoCs), called DFDS, is presented. The key design points in DFDS are: (i) assessing the total waiting cycles of a memory request in NoC and considering it as a metric in arbitration. For this purpose waiting cycles of a memory request are put in an additional flit in a packet and are updated while traversing the NoC, and (ii) proposing a semi-dynamic virtual channel allocation to provide in-order memory requests to memory controllers (MCs). Consequently, we use a simple scheduling algorithm in MCs, instead of complex algorithms. To validate our approach, we apply synthetic and real workload from Parsec benchmark suite. The results show effectiveness of our approach, as we reduce the waiting time of memory requests by up to 15%.  相似文献   

18.
    
Radio frequency identification (RFID) is a powerful technology that enables wireless information storage and control in an economical way. These properties have generated a wide range of applications in different areas. Due to economic and technological constrains, RFID devices are seriously limited, having small or even tiny computational capabilities. This issue is particularly challenging from the security point of view. Security protocols in RFID environments have to deal with strong computational limitations, and classical protocols cannot be used in this context. There have been several attempts to overcome these limitations in the form of new lightweight security protocols designed to be used in very constrained (sometimes called ultra‐lightweight) RFID environments. One of these proposals is the David–Prasad ultra‐lightweight authentication protocol. This protocol was successfully attacked using a cryptanalysis technique named Tango attack. The capacity of the attack depends on a set of boolean approximations. In this paper, we present an enhanced version of the Tango attack, named Genetic Tango attack, that uses Genetic Programming to design those approximations, easing the generation of automatic cryptanalysis and improving its power compared to a manually designed attack. Experimental results are given to illustrate the effectiveness of this new attack.  相似文献   

19.
    
There has been considerable interest in predicting the properties of nitro‐energetic materials to improve their performance. Not to mention insightful physical knowledge, computational‐aided molecular studies can expedite the synthesis of novel energetic materials through cost reduction labours and risky experimental tests. In this paper, quantitative structure–property relationship based on multi‐expression programming employed to correlate the formation enthalpies of frequently used nitro‐energetic materials with their molecular properties. The simple yet accurate obtained model is able to correlate the formation enthalpies of nitro‐energetic materials to their molecular structure with the accuracy comparable to experimental precision.  相似文献   

20.
    
The whole computer hardware industry embraced the multi‐core. The extreme optimisation of sequential algorithms is then no longer sufficient to squeeze the real machine power, which can be only exploited via thread‐level parallelism. Decision tree algorithms exhibit natural concurrency that makes them suitable to be parallelised. This paper presents an in‐depth study of the parallelisation of an implementation of the C4.5 algorithm for multi‐core architectures. We characterise elapsed time lower bounds for the forms of parallelisations adopted and achieve close to optimal performance. Our implementation is based on the FastFlow parallel programming environment, and it requires minimal changes to the original sequential code. Copyright © 2013 John Wiley & Sons, Ltd.  相似文献   

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