Fault Models and Test Procedures for Flash Memory Disturbances

Disturbances are special type of faults that are unique to flash memories. Causes of the disturbances are defects within the insulating layers of the memory element. These defects result in abnormal behavior of a memory cell under specific conditions. This paper describes characteristics of these defects as well as their manifestation as DC-Programming, DC-Erasure, and Drain Disturbance. We develop fault models to capture the behavior of faulty flash memories. We introduce three different fault models based on the underlying defects in a memory cell. These models are: Simple, Exclusive and General Fault model. Further, we develop test algorithms that detect disturbance faults under each of the fault models. The test algorithms reported in this paper for the simple fault model for each type of disturbance require optimal number of program, read, and flash operations; where as the algorithms for the remaining two fault models require near optimal number of these operations.     

Analysis and test procedures for NOR flash memory defects

Widespread use of non-volatile memories, especially flash memories, in diverse applications such as in mobile computing and system-on-chip is becoming a common place. As a result, testing them for faults and reliability is drawing considerable interest of designers and researchers. One of the most predominant failure modes for which these memories must be tested is called disturb faults. In this paper, we first analyze different defects that are responsible for disturb faults using a 2-dimension device simulator. We determine the impact of various defects on cell performance and develop a methodology based on channel erase technique to detect these defects. Our tests are efficient and can be converted to march tests prevalently used to test memories. We also propose a very low cost design-for-testability approach that can be used to apply the test technique developed in this paper.     

Quick address detection of anomalous memory cells in a flash memorytest structure

A novel scheme for quick address detection of anomalous memory cells having the highest and lowest threshold voltages in a flash memory test structure is described. A test structure with a large memory cell array has been developed to evaluate reliability of flash memory cells before fabrication of a new generation of flash memory devices. In this test structure, each terminal branch of a tree-structured column selector is connected to each bitline of the array. And a simple threshold voltage distribution monitor circuit (VTDM) which we have already proposed is connected to the other end of the bitlines. A proposed Multi-Address Scanning Scheme (MASS) is performed by the tree-structured column selector with monitoring the output of VTDM. The detection time has been reduced to 1.12% in the case of 2048 columns. This novel scheme is suitable for performing reliability tests, such as program/erase endurance test and data retention test     

The design, analysis, and development of highly manufacturable 6-T SRAM bitcells for SoC applications

We present here an extensive static random access memory (SRAM) bitcell development methodology that has led to the qualification and production of the smallest 6-T SRAM bitcell reported in 0.13-/spl mu/m CMOS technology. No additional processing steps were employed in accomplishing this result. Such a methodology is being extended also to subsequent technology generations. The development efforts included the electrical evaluation of several candidate 6-T SRAM bitcell architectures for both high-density and high-speed applications. Based on the electrical evaluations, the chosen cell architectures were incorporated in silicon and verified for their robustness with respect to critical design rules, yields and reliability. The methodology for optical proximity correction for bitcell development has been described here. Minor process enhancements to ensure compatibility of the overall process flow with the SRAM bitcells are described. The use of SRAM-specific electrical test structures serves an important role in validating the electrical performance and confirming the robustness of the bitcells in a manufacturing environment. The monitoring of V/sub ddmin/, the minimum voltage at which the memory is functional was used to drive overall process improvements and reliability. Lastly, measurements of soft error rates demonstrated excellent immunity of the bitcells to single event upsets.     

Gate stress effect on low temperature data retention characteristics of split-gate flash memories

In modeling post-cycling low temperature data retention (LTDR) characteristics of split-gate flash memories, gate stress is used to accelerate the charge gain effect responsible for bit cell current reduction among tail bits. To determine the adequate stress condition, various gate stress voltages are performed to enhance the charge gain effect of the flash memory cells. In addition, by analyzing the leakage mechanism and the data retention behavior of cells under gate stress conditions, reliability tests can be completed in a much shorter period and still provide accurate lifetime prediction for embedded memory products.     

非挥发性记忆体Read Disturb测试方法的研究

DDF是一种高容量的NAND Flash。以DDF产品为例,研究和讨论了它的Read Disturb测试方法。受测试时间的限制,只能选择局部的存储区间进行DDF的Read Disturb测试。这样局部区间的测试结果是否能够代表整个芯片的性能,设计了一套实验,对这个课题进行了研究和讨论。依据非挥发性记忆体产品的特性,主要以阈值电压的分布为参考来评价DDF芯片性能的一致性和性能恶化趋势的一致度。最后的实验结果证明了这种测试方法的正确性和合理性。这种分析方法也可以用于其他非挥发性记忆体产品的其他可靠性测试项目的评估。     

A new technique for hot carrier reliability evaluations of flashmemory cell after long-term program/erase cycles

In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N_it) and oxide trap charges (Q_ox) under both channel-hot electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N_it and Q_ox. Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes     

Cycling endurance of NOR flash EEPROM cells under CHISEL programming operation - impact of technological parameters and scaling

The impact of technological parameter (channel doping, source/drain junction depth) variation and channel length scaling on the reliability of NOR flash EEPROM cells under channel initiated secondary electron (CHISEL) programming is studied. The best technology for CHISEL operation has been identified by using a number of performance metrics (cycling endurance of program/erase time, program/disturb margin) and scaling studies were done on this technology. It is explicitly shown that from a reliability perspective, bitcell optimization for CHISEL operation is quite different from that for channel hot electron (CHE) operation. Properly optimized bitcells show reliable CHISEL programming for floating gate length down to 0.2 /spl mu/m.     

Statistical simulations for flash memory reliability analysis and prediction

In this paper, through the use of a recently proposed statistical model of stress-induced leakage current, we will investigate the reliability of actual flash memory technologies and predict future trends. We investigate either program disturbs (namely gate and drain disturbs) and data retention of state-of-the-art flash memory cells and use this model to correlate the induced threshold voltage shift to the typical outputs coming from oxide characterization, that are density, cross section, and energy level of defects. Physical mechanisms inducing the largest threshold voltage (V/sub T/) degradation will be identified and explained. Furthermore, we predict the effects of tunnel oxide scaling on flash memory data retention, giving a rule of thumb to scale the tunnel oxide while maintaining the same retention requirements.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

手持设备中焊垫材料对闪存芯片可靠性的影响

为提高用于手持设备中闪存芯片的可靠性,防止跌落的冲击力对芯片的破坏性伤害,利用试验方法及数理统计分析法对焊垫材料进行研究,为芯片制造商在选择焊垫材料时提供有益的参考。具体针对焊垫涂层为Ni/Au和OSP两种材料,跌落测试条件的严格度依次为H,G,B,F,A,E,D和C,每种样品的数量为45件,每件样品重复跌落100次。通过累积故障百分比与跌落次数的量化图解可知:Ni/Au PF的抗冲击能力较差,在H跌落测试下的故障频率是38%;而OSP PF的抗冲击能力良好,在测试条件B和测试条件F下未见故障产生。     

55 nm SONOS闪存单元的1/f噪声特性研究

基于55 nm ULP CMOS工艺来制备SONOS闪存单元,并通过1/f噪声测试等方式对测试单元的器件特性进行表征。基于1/f噪声表征和转移特性,分析了编程态和擦除态下SONOS闪存单元内部缺陷水平的变化规律与机制。针对1/f噪声与亚阈值特性的缺陷水平出现矛盾的现象,引入NBTI中的双阶段模型进行阐述,进一步分析1/f噪声测试环节对SONOS器件的影响。     

A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory

This paper presents a new read and write assist technique to enable lower voltage operation for Static Random Access Memory (SRAM). The ability to scale the operating voltage with frequency of the chip has big impact on power consumption (Pαv²). The lower end of the operating voltage (V_ddmin) for most chips is determined by the stability of the SRAM cell. The new technique uses a contention-free circuit to generate a Reduced Voltage Swing (RVS) on the wordline (VWL) and selectively reduce the supply to the bitcell (V_ddmem) during write. The required VWL and bitcell voltages are programmable and controllable to adapt to performance and yield requirements. An 8 KB memory test-chip was designed to demonstrate this technique in a low-leakage 45 nm process technology. Results show a 7 to 19% improvement in V_ddmin depending on the process corner, which translates into 14–40% reduction on active power. The proposed technique has 4% area overhead and minimal impact to speed.     

Reliable extraction of cycling induced interface states implementing realistic P/E stresses in reference cell: comparison with flash memory cell

The cycling induced interface states in floating-gate EEPROM cells are reliably extracted by implementing accurate program/erase stresses in the reference cell. The interface states measured directly from the memory cell via charge pumping are shown different from those obtained conventionally from the reference cell. The reasons for these different levels of extraction are elucidated and a new method is presented for accurate determination of interface trap density. The technique is based on introducing the equivalent gate voltage with offset voltage at the reference cell by which to simulate realistically the cycling stresses as occur in the flash memory cell itself.     

An efficient management scheme for updating redundant information in flash-based storage system

Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as a storage media in embedded and computer system environments. However, there are many shortcomings in flash memory such as potentially high I/O latency due to erase-before-write and poor durability due to limited erase cycles. To address these performance and reliability anomalies, many large-scale storage systems use redundancy-based parallel access schemes such as RAID techniques. However, such redundancy-based schemes incur high overhead due to generating and storing redundancy information, especially in flash-based storage systems. In this paper, we propose a novel and performance-effective approach using a redundancy-based data management scheme in flash storage, called Flash-aware Redundancy Array. The proposed technique not only reduces the redundancy management overhead by performing redundancy update operations during idle periods, but also provides a preventive mechanism to recover data from unexpected read errors occurring before such redundancy update operations finish. From the experiments, we found that the proposed technique improves flash-based storage systems by 19% in average execution time as compared to other redundancy-based approaches.     

闪速存储器的研究与进展

介绍了闪速存储器的发展历史,分析了闪速存储器单元及电路的工作原理,并就“与非”结构闪速存储器进行探讨,最后讨论了在闪速存储器中应用的误差矫正码／电路和深亚微米（０．２５μｍ）闪速存储器技术。     

一个描述硅原子团簇退火行为的模型

在考虑硅原子团簇的尺寸对其俘获半径的影响的基础上提出了一个改进的模型,来描述团簇的退火行为,并给出了点缺陷的表面复合速率的表达式.为了验证此模型,给出了动力学蒙特卡洛方法的模拟结果,模拟结果与实验结果相吻合.通过表面复合速率的模拟结果和模型的对比,模型得到了验证.分析表明团簇尺寸对其退火行为有明显的影响     

Cost-effective integration of an FN-programmed embedded flash memory into a 0.25 μm SiGe:C RF-BiCMOS technology

 This paper presents a process technology for cost-effective integration of low-power flash memories into a 0.25 μm, high performance SiGe:C RF-BiCMOS process. Only four additional lithographic steps are used on top of the baseline BiCMOS process, leading to in total 23 mask levels for the BiCMOS/embedded flash process. Uniform-channel Fowler-Nordheim programmable and erasable stacked-gate cells, suitable for medium density (∼Mbit) memories, are demonstrated. Peripheral high-voltage transistors, with >10 V breakdown voltage, are integrated without additional mask steps on top of the flash cell integration. The flash memory integration is modular and has negligible impact on the original CMOS and HBT device parameters.     

Synthesis of Native Mode Self-Test Programs

Recent studies show that at-speed functional tests are better for finding realistic defects than tests executed at lower speeds. This advantage has led to growing interest in design for at-speed tests. In addition, time-to-market requirements dictate development of tests early in the design process. In this paper, we present a new methodology for synthesis of at-speed self-test programs for microprocessors. Based on information about the instruction set, this high-level test generation methodology can generate instruction sequences that exercise all the functional capabilities of complex processors. Modern processors have large memory modules, register files and powerful ALUs with comprehensive operations, which can be used to generate and control built-in tests and to evaluate the response of the tests. Our method exploits the functional units to compress and check the test response at chip internal speeds. No hardware test pattern generators or signature analyzers are needed, and the method reduces area overhead and performance impact as compared to current BIST techniques. A novel test instruction insertion technique is introduced to activate the control/status inputs and internal modules related to them. The new methodology has been applied to an example processor much more complex than any benchmark circuit used in academia today. The results show that our approach is very effective in achieving high fault coverage and automation in at-speed self-test generation for microprocessor-like circuits.     

Effects of the Localization of the Charge in Nanocrystal Memory Cells

In this paper, we present a peculiar characteristic of nanocrystal (NC) memory (NCM) cells: The programming (P) windows measured in linear and subthreshold regions are different. A floating-gate flash memory cell with a similar structure does not show the same behavior, and the P window (PW) is independent of the current level of the extrapolation, as expected. By performing 2-D TCAD simulations, we demonstrated that this characteristic of NCM cells is due to the localization of the charge into the NCs. We investigate the correlation between the difference of the PWs in linear and subthreshold regions and the number, width, and position of the NCs.