保持PC安全、安静和冷却的热管理技术

引言最新个人电脑的工作速度已经超过2GHz。伴随这惊人速度而来的是CPU和外围设备所产生的大量热量。降温风扇通常用来驱散这些过量的热量,但是风扇会增加音频噪声。降低CPU内核的电压和系统时钟能够减少热量耗散,但是这是以牺牲工作性能为代价的。最新的系统和热监视器件整合了复杂的温度监视器、电压监视器和风扇控制功能,使所有参数达到平衡并且保持个人电脑的冷、静和安全。图1是一个典型系统的配置方框图。温度测量测量温度最理想的地方是系统中的最热点。可以是CPU或者是电源、内存、硬盘、显卡这样的外围设备。某些热量监视器提…     

热功率信号下芯片温度动态响应及热特性分析

针对电子元件在瞬态传热中的热惯性问题,对芯片在热功率信号作用下的温度动态响应特性进行识别。根据芯片温度对芯片发热功率的阶跃响应曲线,求得芯片上关键点的传递函数;根据芯片温度的方波响应曲线和正弦响应曲线,重点对热功率信号给芯片造成的温度冲击与信号周期之间的关系进行分析。该研究对提高电子元件抵抗热冲击和热疲劳的能力具有指导意义。     

汽车LED为电源管理带来机遇与挑战

引言 过去10年来,汽车中的电子系统在数量和电子控制、车载多媒体系统及娱乐系统的复杂性等方面都有了巨大的飞跃.展望未来,预计汽车电子系统还将以更快的速度发展.根据市场调研公司AlliedBusiness Intelligence的预测,到2007年,全球汽车半导体市场将从123亿美元(2004年)增长到170亿美元.Strategy Analytics公司也预测,到2008年,汽车电子系统在汽车总成本中所占份额将从目前的20%增长到30%.     

LED封装的热控制优化设计

基于某型LED模块的实验结果,从热膨胀匹配、冷却技术的选择、发光效率、焊料及硅胶选择等方面对大功率LED的热控制问题进行了优化设计。实验结果表明,优化设计后的大功率LED的转换效率和光通量等指标都有了一定程度的改善。     

高功率LED热管理方法研究最新进展

LED芯片结温的高低直接影响其出光效率、工作寿命和可靠性。在分析系统各个环节热阻的基础上,详细评述了高功率LED产品从芯片到系统级的热管理研究新动向,包括:自然对流冷却,采用压电风扇、电离方法所进行的强迫空气对流冷却,采用水、液态金属作为冷却工质的液冷方法,采用热管实现的相变冷却,采用热电片进行的固态冷却方案以及利用热电片对余热进行回收利用的热管热回收方案和液体金属冷却方法。并在上述基础上提出了发展更高功率密度LED热管理方法的关键科学问题。     

功率型LED芯片的热超声倒装技术

结合功率型GaN基蓝光LED芯片的电极分布,在硅载体上电镀制作了金凸点,然后通过热超声倒装焊接技术将LED芯片焊接到载体硅片上.结果表明,在合适的热超声参数范围内,焊接后的功率型LED光电特性和出光一致性较好,证明了热超声倒装焊接技术是一种可靠有效的功率型光电子器件互连技术.     

电源技术日新月异,高集成度带来成本和上市时间优势

随着半导体技术的进步,电源管理器件内部集成了越来越多的元件和功能,其应用涉及各个领域.一般的系统已经集成10个甚至更多不同的电源管理功能,它们不仅提供各种类型的电压,还提供多种系统支持.最初的集成是尽量缩小分立电源器件体积,现在则需要把电源整合成一颗或少数几颗电源管理器件.     

迎接ASON网络管理的挑战

自动交换光网络（ASON）技术是当前光网络领域研究的热点技术，但是有关ASON管理平面的研究工作和标准化才刚刚起点，从网络管理的角度描述了ASON的特点，分析了对ASON的传送平面和控制平面的管理要求，其中对控制平面的管理要求做了重点讨论，最后提出了现行的ASON网络管理方案，并针对不同的用户角色提出了建议。     

智能电网/电表芯片成创新热点

从去年上半年开始。智能电表渐渐成为徼控制器（MCU）业的应用热点，几大MCU公司竟相发布颉产品。不久前，飞思卡尔、ADI和NXP公司上演了新产品秀。     

Scheduling Tests for 3D Stacked Chips under Power Constraints

This paper addresses Test Application Time (TAT) reduction under power constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the TAT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure and propose a test scheduling approach to reduce TAT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant savings in TAT.     

Thermal Management of On-Chip Caches Through Power Density Minimization

Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can be suboptimal when thermal effects are considered. Then, we propose a thermal-aware cache power-down technique that minimizes the power density of the active parts by turning off alternating rows of memory cells instead of entire banks. The decrease in the power density lowers the temperature, which then exponentially reduces the leakage. Thus, leakage power of the active parts is reduced in addition to the power eliminated from the parts that are turned off. Simulations based on SPEC2000, NetBench, and MediaBench applications in a 70-nm technology show that the proposed thermal-aware architecture can reduce the total energy consumption by 53% compared to a conventional cache, and 14% compared to a cache architecture with thermal-unaware power reduction scheme. Second, we show a block permutation scheme that can be used during the design of the caches to maximize the distance between blocks with consecutive addresses. Because of spatial locality, blocks with consecutive addresses are likely to be accessed within a short time interval. By maximizing the distance between such blocks, we minimize the power density of the hot spots in the cache, and hence reduce the peak temperature. This, in return, results in an average leakage power reduction of 8.7% compared to a conventional cache without affecting the dynamic power and the latency. Overall, both of our architectures add no extra run-time penalty compared to the thermal-unaware power reduction schemes, yet they result in a significant reduction in the total energy consumption of a cache     

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm² /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm². Coolers of this design should be able to cool chips with average power densities of 400W/cm² or more     

电子行业标准《小功率LED芯片技术规范》解读

重点介绍了《小功率LED芯片技术规范》标准的编制背景、原则、标准结构和技术内容,对该标准的主要技术内容进行了说明和解读.     

大功率芯片+DCB焊接的改良及应用

介绍了功率器件及芯片与它们结合部件DCB和基板的焊接同时完成。用真空方法能够把焊接空洞率降到低于1%。同时介绍了一台真空焊接系统模型和它的工艺过程及机械结构。最后提出了存在的问题。     

节省成本、功耗和电路板空间的处理器伴随芯片

为削减成本和减少电路板面积, 半导体制造商们正在给原来的处理器配置新功能。一类基于先进制造工艺、 称为“处理器伴侣”的最新产品,它们将种类更为繁多的可编程器件和存储器结构阵列集成到一起,其封装比以前更小,从而更好的实现了对电路板空间的利用,降低了功耗和成本。 Ramtron去年秋天推出其FM31x处理器伴随芯片,该2.7V～5.5V器件集成了一个加强的微处理器(MPU)监控器(supervisor),一个实时时钟(RTC),两个16bit非易失性事件计数器,一个可锁定的64bit序列号区和一个用于早期电源故障中断的比较器以及其他功能,其中一个重要特性就是4kbit～256kbit的非易失性 FRAM(FerroelectronicRandom　Access　Memory,铁电随机存储器)。 监控器带有一个可编程低 VDD 复位功能,一个手动复位功能和可编程看门狗定时器。Ramton 认为其采用14pinSOIC封装的处理器伴随芯片能够取代至少3 个或多达 5 个分立元件。FM31x 等器件一般能与任何一种存储器共同使用,并接受任何一种编程语言。 在其他此类新产品中,Xicor 的X45620是一种集成化...     

Response Surface Based Optimization Approach for Thermal Placement Design of Chips in Multiple-Chip Modules

This paper attempts to perform thermal enhancement of planar multiple-chip modules (MCMs) containing a number of chips of equal and/or unequal power through optimal chip placement design. To achieve the goal, an effective design approach is presented for the thermal design optimization problems in the context of models of placement of chips in MCMs. The approach combines the use of the currently proposed response surface (RS) based methodology, which is an optimization algorithm and a finite element modeling technique. The proposed RS-based methodology is used for creating a macro mathematical expression of the design objective of the thermal optimization problem, i.e., the total chip junction temperature of the system, associated with the design parameters, including the chip location and power. The validity of the mathematical expressions constructed is verified through two approaches. Furthermore, to make the constructed mathematical expression more compact while maintaining the associated solution accuracy, the backward variable elimination technique is employed. The effectiveness of the proposed design optimization methodology is demonstrated through several design case studies involving planar plastic ball grid array type MCMs. It is found that the proposed RS-based methodology could accurately define the macro mathematical model of the total system chip junction temperature in terms of the chip location and power. In addition, results show that the current optimal chip placement design can provide a minimal system temperature.     

功率管理实现最优功率设计

为了实现目前的功率管理目标,需要采取一种全面的功率管理方法,下至晶体管,上至全芯片技术,悉数包含在内。     

大功率LED散热技术和热界面材料研究进展

LED结温的升高将造成发光强度降低、发光主波长偏移、寿命降低等不利影响,开发高效、紧凑、低成本、高可靠性的散热技术是LED的重点研究内容之一。总结了目前大功率LED不同类型散热技术的原理及其研究现状,包括自然对流、风冷、液冷、热管和热电制冷等,分析了各种散热技术的优缺点。并介绍了目前LED常用的几种热界面材料,指出碳纳米管是一种非常有潜力的热界面材料。     

动力电池热管理中半导体制冷技术的应用探析

动力电池是电动汽车的有机组成部分,能够有效提升热能管理的质量,使电动汽车更满足生态文明建设需求。而在动力电池热管理中引入半导体制冷装置,可以有效增强电池的使用寿命和效能质量,提升电池产品的应用价值。而在科技蓬勃发展的背景下,将半导体制冷与电磁热管理相融合,逐渐成为我国电动汽车的研发方向及主流渠道。本文结合半导体制冷在动力电池中的应用契机,明确半导体制冷的基本原理与计算公式,提出相应的应用策略。