数字VLSI电路测试技术-BIST方案

分析了数字VLSI电路的传统测试手段及其存在问题,通过对比的方法,讨论了内建自测试(BIST)技术及其优点,简介了多芯片组件(MCM)内建自测试的目标、设计和测试方案。     

A RF front-end for DVB-SH based on current conveyors

Inductors are used extensively in Radio Frequency Integrated Circuits to design matching networks, load circuits of voltage controlled oscillators, filters, mixers and many other RF circuits. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this paper a new methodology for designing the RF frontend necessary for the DVB-SH in a 90 nm CMOS technology based on the use current conveyors (CC) is presented. The RF frontend scheme is composed of a second generation CC (CCII) LNA with asymmetric input and output, an asymmetric to differential converter, and a passive differential mixer followed by two CCII transimpedance amplifiers to obtain a high gain conversion. Measurements show a conversion gain of 20.8 dB, a 14.5 dB noise figure, an input return loss (S11) of −14.3 dB and an output compression point of −3.9 dBm. This combination draws 28.4 mW from a ±1.2 V supply.     

A synthesis methodology for ECL circuits based on mixed voltage-current representation

This paper presents a synthesis methodology for ECL circuits based on a mixed voltage-current signal representation and operation defined on the voltage and current signals. The ideas presented in this paper are then demonstrated on the design of an BCL 1-bit full adder. The paper concludes by presenting an algebraic system which is suitable for current signal representation and operation on currents.     

Unified built-in self-test for fully differential analog circuits

The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

RF Testing on a Mixed Signal Tester

In this paper, testing of radio frequency (RF) devices with mixed-signal testers is discussed. General purpose automatic test equipment (ATE) will be used. In this paper, a more universal test structure utilizing RF building blocks is proposed. A global positioning system (GPS) device is used as an example to illustrate how to develop the RF test plan with this usage. The test plan developed includes fast, cost-effective and dedicated circuitry.

用于315/433MHz超再生接收机的射频前端关键技术

采用0.5μm CMOS工艺实现了用于315/433MHz超再生无线接收机的射频前端电路,包括射频放大器和超再生振荡器。文中提出了一种改进型有源电感,提高了射频放大器中谐振回路的品质因数。阐述了振荡器的自偏置效应以及振荡器输出信号幅度和电流源的关系,在此基础上实现了适用于包络检波的差分结构超再生振荡器。测试结果显示,电源电压范围为2.5V~5V,电流小于2.5mA,系统接收灵敏度优于-90dBm。     

A dual-band reconfigurable direct-conversion receiver RF front-end

6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm2.     

一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

用于多相和正交信号产生的RF互耦振荡器原理

文章证明了以一定方式相互耦合的多个相同子系统构成的系统在一定务件下能够产生多相或正交振荡信号。根据这一理论，作为例子，给出了一个RC多相互耦振荡器，并推导出了其保持稳定振荡的务件。此外，对于四相位，即正交相位，的情况，也给出了具体的数值结果，与前面的理论分析相一致。     

RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique

The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to architect a RF calibration scheme for DfT chain using DC- instead of RF (GHz) stimuli. The use of DC stimuli relaxes the package design and on-chip routing that results in test cost reduction. A DfT circuit (RF detector, Test-ADC, Test-DAC and multiplexers) designed in 65 nm CMOS is used to demonstrate the proposed calibration scheme. The simulation results show that the cumulative variation in a DfT circuit due to process and mismatch can be estimated and successfully calibrated, i.e. 25% error due to process variation in DfT circuit can be reduced to 2.5% provided the input test stimuli is large in magnitude. This reduction in error makes parametric tests feasible to classify the bad and good dies especially before expensive RF packaging.     

Electrical characterization of analogue and RF integrated circuits by thermal measurements

This paper presents a novel technique for measuring the electrical characteristics of analogue circuits, based on measuring the temperature at the silicon surface close to the circuit under test. As a detailed example, the paper analyses how the gain of an amplifier can be observed through temperature measurements. Experimental results validate the feasibility of the technique. Simulated results show how this technique can be used to measure the bandwidth and central frequency of a 2.4 GHz low noise amplifier (LNA) designed in a 0.35 μm standard CMOS technology.     

A CMOS adaptive RF front-end receiver for wireless applications

The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log?₂ N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.     

Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current

In this paper we have investigated a unified and simultaneous fault detection method for mixed-signal integrated circuits. The method is based on the analysis of the power-supply current through the circuit under test. The analysis has been done paying attention to the dynamic behaviour of the power-supply current, in order to avoid measurement problems related to the large amount of quiescent current drop across many analog blocks.The analysis of the dynamic power-supply current entails certain problems related to the complexity of the measurement process, especially those due to the high speed of the current transients. These problems have been addressed by considering a design for test procedure based on the use of built-in dynamic current sensors.The goal of the design for test methodology proposed is to represent the Iddt through the mixed-signal IC under test by a digital signature. The paper presents some advantages of this approach such as a good tolerance to cross-talk noise and the need for only a conventional digital tester on the complete mixed-signal IC for fault detection. The analysis is illustrated with some test results.     

An effective logic BIST scheme based on LFSR-reseeding and TVAC

An effective logic built-in self-test scheme aiming at reducing the area overhead of IC testing and improving the fault average is proposed, which combines strategies of linear feedback shift register (LFSR)-reseeding with test vectors applied by circuit-under-test itself (TVAC). LFSR-reseeding technology is first applied to decrease the size of test set and the number of interior feedback wires, while TVAC technology is applied to decrease the number of stored seeds. An efficient LFSR-reseeding algorithm and a modified quick judgment method for path search are proposed. Experimental results for ISCAS 85 benchmarks demonstrate that the proposed method reduces the number of interior feedback wires more than 50% on average and can achieve full fault coverage with much less groups as well as area overhead compared with previous TVACs.     

输出功率-3dBm的射频发射前端在802.11g中的应用

A 2.4 GHz,direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals.The front-end output power is -3 dBm while the corresponding EVM is -27 dB which is necessary for the 802.1 1g standard of EVM at-25 dB. With the adopted gain control strategy the output power changes from -14.3 to -3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process.A power detector indicates the output power and delivers a voltage to the baseband to control the output power.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

无线系统中的RF器件与电路

介绍了下一代无线系统中存在的问题 ,分别概述了无线系统中 RF器件与电路的发展与现状。     

一种新的SOI射频集成电路结构与工艺

立足于与常规CMOS兼容的SOI工艺，提出了电子束／I线混合光刻制造SOI射频集成电路的集成结构和工艺方案。该方案只使用9块掩模版即完成了LDMOS、NMOS、电感、电容和电阻等元件的集成。经过对LDMOS、NMOS的工艺、器件的数值模拟和体硅衬底电感的初步实验，获得了良好的有源和无源器件特性，证明这一简洁的集成工艺方案是可行的。     

基于FPGA的超声波传感器前端电路设计

超声波传感器广泛应用于风速、风向的测量,前端电路的设计直接关乎系统性能的好坏.为达到稳定的驱动效果,驱动电路采用了低压驱动方式.为能接收稳定、准确的超声波信号,设计了接收及信号处理电路,进行接收抗干扰限幅处理、前置放大、带通滤波、自动增益控制放大和电压比较,将所接收的超声波交变电压信号转换成可供FPGA 直接使用的数字信号.实验结果验证,各个电路模块的设计均满足系统要求.