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国际上权威的通用布局布线工具(Versatile Place and Route tool,VPR)所支持的开关盒(Switch Box,SB)结构限定在Disjoint,Wilton和Universal3种类型,并且通道内同种类型的互连线必须相邻排列。针对这两个约束,该文提出了FPGA(Field Programmable Gate Array)层次化通用开关盒模型,可涵盖FPGA中的任意开关盒结构,并基于这种模型,提出了具有更高布通率的新型开关盒结构JSB(Joint Switch Box,JSB),与Disjoint,Wilton和Universal结构相比,布通率分别提高了10.1%,3.3%和4.6%;还通过优化分布FPGA中互连线,大幅度减小了电路延时,在相同工艺参数和相同开关盒的条件下,比VPR的布线时延关键路径平均缩短了10.4%。 相似文献
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FPGA主要由两个基本部分组成,一是可配置逻辑部件,另一部分就是互联网络,负责对可配置逻辑块间的通信。FPGA内部大约80%的晶体管都是作为可编程开关和缓冲器来完成可编程路由网络工作的。文中主要对出现错误的开关盒阵列中可执行的路径数量进行评估,并且使用算法找到合适的路径,避开错误。 相似文献
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研究了新型的FDP FPGA电路结构及其设计实现.新颖的基于3输入查找表的可编程单元结构,与传统的基于4输入查找表相比,可以提高约11%的逻辑利用率;独特的层次化的分段可编程互联结构以及高效的开关盒设计,使得不同的互联资源可以快速直接相连,大大提高了可编程布线资源效率.FDP芯片包括1600个可编程逻辑单元、160个可用IO、内嵌16k双开块RAM,采用SMIC 0.18μm CMOS工艺全定制方法设计并流片,其裸芯片面积为6.104mm×6.620mm.最终芯片软硬件测试结果表明:芯片各种可编程资源可以高效地配合其软件正确实现用户电路功能. 相似文献
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FPGA开关盒的设计主要关注于一种跨度互联线相互连接的研究。在这些开关盒中,不同跨度的互联线相互分隔和独立,在一定程度降低了互联的性能和利用率。提出了一种可以将不同跨度互联线通过可编程开关进行连接的混合型开关盒设计思想,提高10%互连结构的性能,而不会增加芯片面积以及功耗。此设计方法在复旦大学FDPFPGA芯片互联结构中得以应用。 相似文献
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硬件结构及电子设计的质量是决定FPGA性能的两个重要因素。针对这两个方面,提出了一种通用的FP-GA芯片I/O互连结构,利用"回线"的终端互补原理对各种互连线的悬空终端进行连接。根据所提出的I/O互连结构的特点,在较少编程点的前提下,减少传输管级联个数,对多路选择器和缓冲器进行优化,提出了一种节省芯片面积且速度较快的基于MUX-Buffer结构的布线开关。该结构已在FPGA芯片中实现,对I/O互连的仿真及测试结果表明,所提出的结构及电路实现具有很好的延时可预测性,与常规MUX结构相比,面积-延时乘积降低了10%左右。 相似文献
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本文介绍了印刷电路板的基本设计方法和原则要求。并以Protel软件为例详细分析了高频电路中的布线技巧。 相似文献
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现场可编程门阵列(FPGA)是一种可编程逻辑器件,由成千上万个完全相同的可编程逻辑单元组成,周围是输入,输出单元构成的外设。制造完成后,FPGA可以在工作现场编程,以便实现特定的设计功能。典型设计工作包括指定各单元的简单逻辑功能,并选择性地闭合互连矩阵中的一些开关。为确保正常工作, 相似文献
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为实现红外图像坏元修正FPGA(field programmable gate array)的快速验证,提高测试覆盖性,设计了基于SV-DPI(SystemVerilog-direct programming interface)的FPGA自动化验证平台。采用DPI(direct programming interface)编程接口技术,实现了SystemVerilog平台调用C++编程语言,构建了针对红外图像坏元数据的生成和检测修正模型,建立了两种语言在事务级(transaction level)模型的通信。结果表明相对于传统验证方法,该平台结构简单,可以快速实现激励产生、参考模型构建、测试结果自动比对等功能,实现了红外图像坏元检测与修正FPGA的自动化测试,功能覆盖率达到100%,有效缩短FPGA测试平台搭建和调试周期,提高了测试效率和测试质量。 相似文献
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A novel test approach for interconnect resources(IRs)in field programmable gate arrays (FPGA)has been proposed.In the test approach,SBs (switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns. 相似文献
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Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect
wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing
and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays.
Given a target physical wire length, width, and spacing, the method determines the number, size, and position of buffers required
to obtain the fastest signal velocity for programmable interconnect. While traditional hand-calculations used for ideal repeater
placement can be used, they are not very accurate and ignore practical constraints such as the overhead effects of front-end
multiplexing and driving logic, “finite” wire length, and a discrete number of repeaters. A metric introduced during the design
is the “path delay profile”, or the arrival time of a signal at different points of a long wire. This method is used to design
buffering strategies for interconnect based on 0.5, 2, and 3 mm wire lengths in 180 nm technology. These interconnect designs
are coded into VPR along with an improved timing analyzer which accurately determines the “path delay profile” arrival times.
Using VPR, average critical-path delay is reduced by 19% for 0.5 mm wires and by up to 46% for 3mm wires over previous designs.
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Shahriar MirabbasiEmail: |
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Standaert O.-X. Peeters E. Rouvroy G. Quisquater J.-J. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2006,94(2):383-394
Since their introduction by Kocher in 1998, power analysis attacks have attracted significant attention within the cryptographic community. While early works in the field mainly threatened the security of smart cards and simple processors, several recent publications have shown the vulnerability of hardware implementations as well. In particular, field programmable gate arrays are attractive options for hardware implementation of encryption algorithms,but their security against power analysis is a serious concern, as we discuss in this paper. For this purpose, we present recent results of attacks attempted against standard encryption algorithms, provide a theoretical estimation of these attacks based on simple statistical parameters and evaluate the cost and security of different possible countermeasures. 相似文献