Substrate interconnect technologies for 3-D MEMS packaging

We report the development of 3-dimensional silicon substrate interconnect technologies, specifically for reducing the package size of a MOSFET relay. The ability to interconnect multiple chips at different elevations on a single substrate can significantly improve device performance and size. We present the process development of through-hole interconnects fabricated using deep reactive ion etching (DRIE), with an emphasis on achieving positively tapered, smooth sidewalls to ease deposition of a seed layer for subsequent Cu electroplating. Gray-scale technology is integrated on the same substrate to provide smooth inclined surfaces between multiple vertical levels (>100 μm apart), enabling interconnection between the two levels via simple metal evaporation and lithography. The developments discussed for each technique may be used together or independently to address future packaging and integration needs.     

多晶硅衬底上的RF MEMS开关

在微机械开关与硅IC工艺设计和兼容方面进行了改进,获得了一种可与IC工艺兼容的RFMEMS微机械开关.采用介质隔离工艺技术把这种RFMEMS微机械开关制作在绝缘的多晶硅衬底上,实现了与IC工艺兼容;采用在金属膜桥的端点附近刻蚀一些孔的优化方法,降低了RFMEMS微机械开关的下拉电压.用TE2 819电容测试设备测试开关的电容,测得开关的开态电容、关态电容和致动电压分别为0 32 pF、6 pF和2 5V .用HP875 3C网络分析仪对RFMEMS微机械开关进行了RF特性测试,得出RFMEMS微机械开关在频率1 5GHz下关态的隔离度为35dB ,开态的插入损耗为2dB ,用示波器测得该开关的开关     

多晶硅衬底上的RF MEMS开关

在微机械开关与硅IC工艺设计和兼容方面进行了改进,获得了一种可与IC工艺兼容的RF MEMS微机械开关.采用介质隔离工艺技术把这种RF MEMS微机械开关制作在绝缘的多晶硅衬底上,实现了与IC工艺兼容;采用在金属膜桥的端点附近刻蚀一些孔的优化方法,降低了RF MEMS微机械开关的下拉电压.用TE2819电容测试设备测试开关的电容,测得开关的开态电容、关态电容和致动电压分别为0.32pF、6pF和25V.用HP8753C网络分析仪对RF MEMS微机械开关进行了RF特性测试,得出RF MEMS微机械开关在频率1.5GHz下关态的隔离度为35dB,开态的插入损耗为2dB,用示波器测得该开关的开关速度为3μs.     

射频CO2激光陶瓷基板划片机

介绍了RFCO2 激光器及其对陶瓷基板划片的特点。分析了RFCO2 激光陶瓷基板划片的机理 ;给出了整机总体设计方案。对导光系统的激光束进行了模拟 ,给出了导光系统的光路图及聚焦镜焦平面处的光斑尺寸及能量分布图。整机性能指标达到国外进口机的水平     

Device technologies for RF front-end circuits in next-generation wireless communications

Next-generation high data rate wireless communication systems offer completely new ways to access information and services. To provide higher data speed and data bandwidth, RF transceivers in next-generation communications are expected to offer higher RF performance in both transmitting and receiving circuitry to meet quality of service. The semiconductor device technologies chosen will depend greatly on the tradeoffs between manufacturing cost and circuit performance requirements, as well as on variations in system architecture. It is hard to find a single semiconductor device technology that offers a total solution to RF transceiver building blocks in terms of system-on-chip integration. The choices of device technologies for each constituent component are important and complicated issues. We review the general performance requirement of key components for RF transceivers for next-generation wireless communications. State-of-the-art high-speed transistor technologies are presented to assess the capabilities and limitations of each technology in the arena of high data rate wireless communications. The pros and cons of each technology are presented and the feasible semiconductor device technologies for next-generation RF transceivers can be chosen upon the discretion of system integrators.     

多功能综合射频系统技术综述

介绍了综合射频技术和综合射频传感器的概念、特点和优势,综述了美国海军AMRFC计划、美国空军ISS计划和F-35战斗机的综合射频传感器系统,进一步探讨了多功能综合射频系统的关键技术和发展前景。     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法.这种方法是直接在硅衬底形成间隔的pn结隔离以阻止螺旋电感诱导的涡流.衬底pn结间隔能用标准硅工艺实现而不需另外的工艺.本文设计和制作了硅集成电路,测量了硅集成电感的S参数并且从测量数据提取了电感的参数.研究了衬底结隔离对硅集成电感的品质因素Q的影响.结果表明一定深度的衬底结隔离能够取得很好的效果.在3GHz,衬底pn结隔离能使电感的品质因素Q值提高40%.     

Advanced RF switching and on-board regeneration technologies for digital satellite communications

In this paper, functional blocks of a generic on-board processing payload are identified, and some key technology implementation issues for on-board RF and/or baseband switching, signal regeneration and processing are addressed. The design and performance characteristics of a microwave switch matrix and a 120 Mb/s coherent quadrature phase shift keying demodulator for satellite applications are presented. This hardware is realized with monolithic microwave integration technology. Significant performance improvement and reduction in size and weight, as well as enhanced subsystem reliability, have been demonstrated, making these technologies attractive for flexible communications satellite payload architectures of the future. Transmission analysis is performed to quantify link budget advantages that could be obtained by using on-board regeneration.     

面向5G通信的射频关键技术分析

目前2G通信技术基本已经停用,3G通信技术得到普遍应用,4G通信技术也已经得到广泛推广和使用,通信行业的研究焦点从4G通信技术迅速转移到5G通信技术.本文结合5G通信技术的未来展望,分析了具有发展前景的大规模MIMO技术、毫米波频段移动通信技术、同频全双工技术三项面向5G通信的射频关键技术.     

Reconfigurable RFICs in Si-based technologies for a compact intelligent RF front-end

This paper presents reconfigurable RF integrated circuits (ICs) for a compact implementation of an intelligent RF front-end for multiband and multistandard applications. Reconfigurability has been addressed at each level starting from the basic elements to the RF blocks and the overall front-end architecture. An active resistor tunable from 400 to 1600 /spl Omega/ up to 10 GHz has been designed and an equivalent model has been extracted. A fully tunable active inductor using a tunable feedback resistor has been proposed that provides inductances between 0.1-15 nH with Q>50 in the C-band. To demonstrate reconfigurability at the block level, voltage-controlled oscillators with very wide tuning ranges have been implemented in the C-band using the proposed active inductor, as well as using a switched-spiral resonator with capacitive tuning. The ICs have been implemented using 0.18-/spl mu/m Si-CMOS and 0.18-/spl mu/m SiGe-BiCMOS technologies.     

High Performance RF Passive Integration on a Si Smart Substrate for Wireless Applications

To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6“ Si wafer with a 25 μm thick SiO₂ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 Ω coplanar transmission line (W=50 μm, G=20 μm). Using benzo cyclo butene (BCB) interlayers and a 10 μm Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30‐120, depending on geometrical parameters and inductance values of 0.35‐35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high‐speed wireless LAN applications. The chip sizes of the wafer‐level‐packaged RF IPDs and wire‐bondable RF IPDs were 1.0‐1.5 mm² and 0.8‐1.0 mm², respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand‐held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.     

高低频复合基板研究

高低频复合基板技术是在同一块基板上同时实现低频信号和高频信号的传输.主要介绍了高低频复合基板制造面临的挑战以及高低频复合基板的主要特性.较为详细地介绍了高低频复合基板主要的三种实现方式,即FR4印制电路板与微波印制电路的复合结构、低温共烧陶瓷技术以及液晶聚合物基板.     

Extraction of Substrate Resistance in Bulk FinFETs Through RF Modeling

A new method to extract substrate resistance (R_sub) for small-sized nano-scale metal oxide semiconductor field effect transistors (MOSFETs) including bulk FinFETs is proposed and compared with conventional method. The R_sub's extracted from small-size MOSFETs by using the proposed method are shown to have frequency independent characteristics, unlike those from the conventional method. Proposed equivalent circuit explains well the R_sub behavior with body width. The proposed model showed very good agreement (error in Y₂₂~3%) with three-dimensional device simulation     

The CHIP - A Design Guide for Reducing Substrate Noise Coupling in RF Applications

This article discusses a set of design guidelines to reduce the on-chip substrate noise coupling in RF and mixed signal applications. Measurement data is presented to compare the various signal isolation techniques. A design flow is calibrated to the measured data and is used to expand the design guide to include the effects of the geometrical and electrical parameters of the isolation structures as well as the frequency of operation on the isolation level. A set of guidelines is presented to the reader as a summary of the studied experiments     

射频仿真系统目标模拟关键技术研究

对射频仿真目标模拟系统中扩展目标模拟、宽带捷变频信号模拟、多普勒频率模拟和雷达发射载频获取等关键技术进行了分析,并提出了具体的解决措施。     

硅基螺旋电感的几何参数设计和优化

使用三维电磁场模拟的方法对相同硅衬底结构下不同布图结构的螺旋电感进行了模拟和分析.通过改变电感匝数、电感金属的宽度和间隔以及电感的内径,模拟和分析了电感性能的变化.给出了引起电感性能变化的原因.结果表明优化电感的几何参数可以有效地改善电感性能.得出了一些实用的设计原则,可有效地指导射频集成电路中集成电感的设计.     

Layout Design and Optimization of RF Spiral Inductors on Silicon Substrate

使用三维电磁场模拟的方法对相同硅衬底结构下不同布图结构的螺旋电感进行了模拟和分析.通过改变电感匝数、电感金属的宽度和间隔以及电感的内径,模拟和分析了电感性能的变化.给出了引起电感性能变化的原因.结果表明优化电感的几何参数可以有效地改善电感性能.得出了一些实用的设计原则,可有效地指导射频集成电路中集成电感的设计.     

Substrate Effects on Resonant Frequency of Silicon-Based RF On-Chip MIM Capacitor

This brief presents an analytical model that describes a silicon-based RF on-chip metal-insulator-metal (MIM) capacitor including the parasitics originating from its coupling with backend intermetal dielectric (IMD) scheme and the substrate. Results show that the resonant frequency f_re depends on the intrinsic capacitance, inductance, and substrate effects of the MIM. The model and f_re formula are verified experimentally for several types of MIM capacitors (i.e., high kappa and Si₃N₄ based) integrated on different IMDs (e.g., undoped glass and low kappa). The results also show that for a given C_MIM, if the capacitance density is increased further so that the area is shrunk, and the inductances are reduced to a level that is comparable to the substrate effects from item epsiv₀epsiv_rrho_Si h_eff|SiR₂/h_eff|IMD, then further f_re improvement could be limited