应变Si1-x Gex pMOSFET反型沟道空穴低场迁移率模型

在考虑应变对SiGe合金能带结构参数影响的基础上,提出了一个半经验的应变Sil-xGex/Si pMOSFET反型沟道空穴迁移率模型.在该模型中,给出了迁移率随应变的变化,并且考虑了界面陷阱电荷对载流子的库仑散射作用.利用该模型对室温下空穴迁移率随应变的变化及影响空穴迁移率的因素进行了分析讨论.     

考虑库仑散射屏蔽效应的Si_(1-x)Ge_x pMOSFET低场空穴迁移率模型

在考虑应变对SiGe合金能带结构参数影响的基础上,建立了一个半经验的Si1-xGexpMOSFET反型沟道空穴迁移率模型。该模型重点讨论了反型电荷对离化杂质散射的屏蔽作用,由此对等效体晶格散射迁移率进行了修正。并且详细讨论了等效体晶格散射迁移率随掺杂浓度Nd和组分x的变化。利用该模型,对影响空穴迁移率的主要因素进行了分析讨论。通过模拟得出,增加组分x可以显著提高等效体晶格散射迁移率,从而可以提高PMOSFET的空穴迁移率。     

〈100〉沟道方向对高迁移率双轴应变硅p-MOSFET的作用

双轴应变技术被证实是一种能同时提高电子和空穴迁移率的颇有前景的方法;〈100〉沟道方向能有效地提升空穴迁移率. 研究了在双轴应变和〈100〉沟道方向的共同作用下的空穴迁移率. 双轴应变通过外延生长弛豫SiGe缓冲层来引入,其中,弛豫SiGe缓冲层作为外延底板,对淀积在其上的硅帽层形成拉伸应力. 沟道方向的改变通过在版图上45°旋转器件来实现,这种旋转使得沟道方向在(001)表面硅片上从〈110〉晶向变成了〈100〉晶向. 对比同是〈110〉沟道的应变硅pMOS和体硅pMOS,迁移率增益达到了130%;此外,在相同的应变硅pMOS中,沟道方向从〈110〉到〈100〉的改变使空穴迁移率最大值提升了30%. 讨论和分析了这种双轴应变和沟道方向改变的共同作用下迁移率增强的机理.     

<100>沟道方向对高迁移率双轴应变硅p-MOSFET的作用

双轴应变技术被证实是一种能同时提高电子和空穴迁移率的颇有前景的方法;<100>沟道方向能有效地提升空穴迁移率.研究了在双轴应变和<100>沟道方向的共同作用下的空穴迁移率.双轴应变通过外延生长弛豫SiGe缓冲层来引入,其中,弛豫SiGe缓冲层作为外延底板,对淀积在其上的硅帽层形成拉伸应力.沟道方向的改变通过在版图上45°旋转器件来实现.这种旋转使得沟道方向在(001)表面硅片上从<110>晶向变成了<100>晶向.对比同是<110>沟道的应变硅pMOS和体硅pMOS,迁移率增益达到了130%;此外,在相同的应变硅pMOS中,沟道方向从<110>到(100)的改变使空穴迁移率最大值提升了30%.讨论和分析了这种双轴应变和沟道方向改变的共同作用下迁移率增强的机理.     

应变硅pMOS反型层中空穴迁移率k·p及蒙特卡罗模拟研究

对应变硅pMOS反型层中的空穴迁移率进行了理论研究.使用应力相关的6能带k·p模型,自洽地求解垂直于沟道方向的一维薛定谔方程与泊松方程,获得反型层中二维空穴气的能带结构.采用蒙特卡罗方法对单轴压应力和双轴张应力情况下的空穴迁移率进行了模拟研究,得出了沟道迁移率随垂直于沟道电场变化的曲线,并与常规的非应变硅pMOS迁移率进行了比较.模拟结果显示:无论是单轴压应力还是双轴张应力,都使得空穴迁移率增大.当单轴压应力沿着[110]沟道时,迁移率增大的幅度最大,平均增幅可达到170%左右.     

应变硅pMOS反型层中空穴迁移率k·p及蒙特卡罗模拟研究

对应变硅pMOS反型层中的空穴迁移率进行了理论研究.使用应力相关的6能带k·p模型,自洽地求解垂直于沟道方向的一维薛定谔方程与泊松方程,获得反型层中二维空穴气的能带结构.采用蒙特卡罗方法对单轴压应力和双轴张应力情况下的空穴迁移率进行了模拟研究,得出了沟道迁移率随垂直于沟道电场变化的曲线,并与常规的非应变硅pMOS迁移率进行了比较.模拟结果显示:无论是单轴压应力还是双轴张应力,都使得空穴迁移率增大.当单轴压应力沿着[110]沟道时,迁移率增大的幅度最大,平均增幅可达到170%左右.     

应变Si/(001)Si_(1-x)Ge_x价带结构

应变SiCMOS技术是当前国内外研究发展的重点,在高速/高性能器件和电路中有极大的应用前景。基于(001)面弛豫Si1-xGex衬底上生长的张应变Si的价带E(k)-k关系模型,研究获得了[100]和[001]晶向的价带结构及相应的空穴有效质量。结果表明,与弛豫材料相比,应变引起了应变Si/(001)Si1-xGex价带顶的劈裂,且同一晶向族内沿[001]和[100]两个晶向的价带结构在应力的作用下不再对称,相应的空穴有效质量随Ge组份有规律地变化。价带空穴有效质量与迁移率密切相关,该结论为Si基应变PMOS器件性能增强的研究及导电沟道的应力与晶向设计提供了重要理论依据。     

应变Si_(1-x)Ge_x(001)空穴有效质量各向异性

利用应变Si1-xGex技术提高空穴迁移率是当前国内外关注的研究领域和研究发展重点。基于KP理论框架,研究获得了应变Si1-xGex/(001)Si材料沿不同晶向及各向同性空穴有效质量。结果表明,应变Si1-xGex/(001)Si带边[1-11]、[001]、[1-10]、[-110]和[100]晶向空穴有效质量在压应力的作用下变化明显,其各向异性更加显著。此外,当Ge组份较大时,带边和亚带边空穴各向同性有效质量接近,传统的"重空穴"和"轻空穴"概念失去意义。价带空穴有效质量与迁移率密切相关,该研究成果为Si基应变pMOS器件性能增强的研究及导电沟道的应力与晶向设计提供了重要理论依据。     

硅基不同晶面上的空穴迁移率研究

近年来,金属氧化物半导体场效应晶体管(MOSFET)的特征尺寸减小并进入纳米尺度,为了改善器件的短沟道效应,器件由原来的平面结构改为立体结构。而在立体结构器件中,沟道由不同于传统Si(100)晶面的Si晶面所组成。因此,为了了解不同Si晶面上器件反型层空穴迁移率的变化情况,在不同晶面Si衬底上分别制作了pMOSFET,并研究了器件的空穴迁移率。采用Split C-V方法测试了Si(100),(110),(111)和(112)晶面上器件的空穴迁移率。结果表明,Si(110)晶面上的空穴迁移率最大,Si(112)晶面上<111>沟道方向空穴迁移率比(110)晶面上空穴迁移率小,而略大于(100)和(111)晶面上的空穴迁移率,(100)晶面上的空穴迁移率最小。     

应变Si/SiO2界面对NMOS沟道电子迁移率的影响研究

本文提出全新的半经验应变Si NMOS反型沟道电子迁移率模型，此模型考虑了晶格散射，离化杂质散射，表面声子散射，界面电荷散射以及界面粗糙散射等散射机制对反型沟道电子迁移率的影响，并考虑了反型层电子的屏蔽效应。利用Matlab软件对所建模型进行了模拟，模拟结果与实验数据符合较好。     

Hole transport in UTB MOSFETs in strained-Si directly on insulator with strained-Si thickness less than 5 nm

Hole transport is studied in ultrathin body (UTB) MOSFETs in strained-Si directly on insulator (SSDOI) with a Si thickness down to 1.4 nm. In these Ge-free SSDOI substrates, the Si is strained in biaxial tension with strain levels equivalent to strained-Si on relaxed SiGe, with Ge contents of 30 and 40% Ge. The hole mobility in SSDOI decreases slowly for Si thicknesses above 4 nm, but drops rapidly below that thickness. Relative to silicon-on-insulator control devices of equal thickness, SSDOI displays significant hole mobility enhancement for Si film thicknesses above 3.5 nm. Peak hole mobility is improved by 25% for 40% SSDOI relative to 30% SSDOI fabricated by the same method, demonstrating the benefits of strain engineering for 3.1-nm-thick UTB MOSFETs.     

Tensile-Strained Germanium CMOS Integration on Silicon

Monolithic integration of tensile-strained Si/ Germanium (Ge)-channel n-MOS and tensile-strained Ge p-MOS with ultrathin (equivalent oxide thickness ~14 Aring) HfO₂ gate dielectric and TaN gate stack on Si substrate is demonstrated. Defect-free Ge layer (279 nm) grown by ultrahigh vacuum chemical-vapor deposition is achieved using a two-step Ge-growth technique coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to ~0.67% and exhibits a peak hole mobility of 250 cm²/V ldr s which is 100% higher than the universal Si hole mobility. The gate leakage current is two orders of magnitude lower compared to the reported results on Ge bulk.     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

薄虚拟SiGe衬底上的应变Si pMOSFETs

成功地试制出薄虚拟SiGe衬底上的应变Si pMOSFETs.利用分子束外延技术在100nm低温Si(LT-Si)缓冲层上生长的弛豫虚拟Si0.8Ge0.2衬底可减薄至240nm.低温Si缓冲层用于释放虚拟SiGe衬底的应力,使其应变弛豫.X射线双晶衍射和原子力显微镜测试表明:虚拟SiGe衬底的应变弛豫度为85%,表面平均粗糙度仅为1.02nm.在室温下,应变Si pMOSFETs的最大迁移率达到140cm2/(V·s).器件性能略优于采用几微米厚虚拟SiGe衬底的器件.     

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.     

La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs with high hole mobility and good device characteristics

We have studied high-k La/sub 2/O/sub 3/ p-MOSFETs on Si/sub 0.3/Ge/sub 0.7/ substrate. Nearly identical gate oxide current, capacitance density, and time-dependent dielectric breakdown (TDDB) are obtained for La/sub 2/O/sub 3//Si and La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ devices, indicating excellent Si/sub 0.3/Ge/sub 0.7/ quality without any side effects. The measured hole mobility in nitrided La/sub 2/O/sub 3//Si p-MOSFETs is 31 cm/sup 2//V-s and comparable with published data in nitrided HfO/sub 2//Si p-MOSFETs. In sharp contrast, a higher mobility of 55 cm/sup 2//V-s is measured in La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFET, an improvement by 1.8 times compared with La/sub 2/O/sub 3//Si control devices. The high mobility in Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs gives another step for integrating high-k gate dielectrics into the VLSI process.     

Subband structure and effective mass of relaxed and strained Ge (1 1 0) PMOSFETs

Effective mass and mobility of strained Ge (1 1 0) inversion layer in PMOSFET are studied theoretically in this paper. The strain condition considered in the calculations is the intrinsic strain resulting from growing the Ge layer on the (1 1 0) Si substrate. The quantum confinement effect resulting from the vertical effective electric field is incorporated into the k · p calculation. Various effective masses, such as quantization effective mass, m_z, density of states effective mass, m_DOS, and conductivity mass, m_C, as well as the hole mobility of strained Ge (1 1 0) inversion layer for PMOS under substrate strain and various effective electric field strengths are all investigated.