A wide locking range and low Voltage CMOS direct injection-locked frequency divider

A low voltage and wide locking range injection-locked frequency divider using a standard 0.18-/spl mu/m complementary metal oxide semiconductor (CMOS) process is presented. The wide locking range and the low-voltage operation are performed by adding an injection nMOS between the differential outputs of the divider that contains on-chip transformers which result in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. The measurement results show that at the supply voltage of 0.75-V, the divider free-running frequency is 2.02 GHz, and at the incident power of 0 dBm the locking range is about 1.49 GHz (36.88%), from the incident frequency 3.27 to 4.64GHz.     

18 GHz low-power CMOS static frequency divider

A pseudo-differential latch circuit is investigated. By removing the current source from the conventional source-coupled field-effect-transistor logic (SCFL) structure, the speed of the circuit can be improved. The pseudo-differential D-type flip-flop-based 2:1 static frequency divider, which can operate up to 18 GHz and consumes less than 4 mA from a 1.8 V supply, has been realised in 0.18 /spl mu/m standard digital CMOS technology.     

A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers

A high-frequency divide-by-256–271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchronous counters. The programmable divider using proposed flip-flops is measured in 0.25-μm CMOS technology with the operating clock frequency reaching as high as 4.7 GHz under the supply voltage of 3V.     

A wide-band CMOS injection-locked ring oscillator

An injection-locked ring oscillator fabricated in a 0.18-/spl mu/m CMOS process is presented for high-speed applications. By tuning the free-running frequency, the proposed circuit provides 2:1 and 4:1 frequency division over a wide input frequency range. The measured input frequency range covers 16.7-25.2 GHz and 41.2-46.9 GHz for 2:1 and 4:1 frequency division, respectively. The divider core operates at a 1.8-V supply voltage with a power consumption between 21.0 and 23.8mW for the entire frequency tuning range.     

81.5?85.9 GHz injection-locked frequency divider in 65 nm CMOS

An injection-locked frequency divider (ILFD) using the shunt-series inductive peaking technique is proposed. Fabricated in a 65 nm process, the proposed ILFD and a conventional one have the measured locking range of 81.5-85.9 and 71-77.4 GHz, respectively. Compared with the conventional ILFD, the measured free-running frequency of the proposed one is increased by 12.5 . Both ILFDs have core area of 0.036 mm² and power of 12 mW for a 1.55 V supply without buffers.     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².     

High-speed CMOS frequency divider

A high-speed CMOS frequency divider is proposed. Using fewer transistors and only NMOS transistors in the regenerative circuits of the latches, the frequency divider achieves higher speed through the reduced capacitances at the output nodes and larger transconductance. A device sizing rule for the maximum input frequency is given. The proposed frequency divider is suitable for high-speed operational while consuming a moderate amount of power     

A wide-locking range 6-phase divide-by-3 injection-locked frequency divider

A 6-phase divide-by-3 CMOS injection locked frequency dividers (ILFDs) have been proposed and implemented in a 0.35 μm CMOS process. The ILFD circuits are realised with a 3-stage double cross-coupled CMOS ring oscillator. The self-oscillating voltage controlled oscillator (VCO) is injection-locked by 3th-harmonic input to obtain the division factor of 3. Measurement results show that as the supply voltage varies from 1.2 to 3.5 V, the free-running frequency is from 0.136 to 0.7 GHz. At the incident power of ?5 dBm, the locking range in the divide-by-3 mode is from the incident frequency 0.38–2.31 GHz.     

A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator

A low voltage multiband all-pMOS VCO was fabricated in a 0.18-/spl mu/m CMOS process. By using a combination of inductor and capacitor switching, four band (2.4, 2.5, 4.7, and 5 GHz) operation was realized using a single VCO. The VCO with an 1-V power supply has phase noises at 1-MHz offset from a 4.7-GHz carrier of -126 dBc/Hz and -134 dBc/Hz from a 2.4-GHz carrier. The VCO consumes 4.6 mW at 2.4 and 2.5 GHz, and 6 mW at 4.7 and 5 GHz, respectively. At 4.7 GHz, the VCO also achieves -80 dBc/Hz phase noise at 10-kHz offset with 2 mW power consumption.     

V-band harmonic injection-locked frequency divider using cross-coupled FETs

A V-band 1/2 frequency divider is developed using harmonic injection-locked oscillator. The cross-coupled field effect transistors (FETs) and low quality-factor microstrip resonator are employed as a wide-band oscillator to extend the locking bandwidth. The second harmonic of free-running oscillation signal is injected to the gates of cross-coupled FETs for high-sensitivity superharmonic injection locking. The fabricated microwave monolithic integrated circuit frequency divider using 0.15-/spl mu/m GaAs pHEMT process showed a maximum locking range of 7.4 GHz (from 65.1 to 72.5 GHz) under a low power dissipation of 100 mW. The maximum single-ended output power was as high as -3 dBm.     

A low-voltage,low power divide-by-4 LC-tank injection-locked frequency divider

A low-voltage wide locking range injection-locked frequency divider (ILFD) using a standard 0.18?µm complementary metal-oxide-semiconductor process is presented. The ILFD is based on a differential LC VCO with one injection metal oxide semiconductor field effect transistor (MOSFET) for coupling external signals to the resonator. The low-voltage operation and wide locking range is obtained by boosting the gate voltage swing of the ILFD. Measurements show that at the supply voltage of 0.67?V, the divider's free-running frequency is tunable from 3.91 to 4.22?GHz, and the core power consumption is 1.87?mW. At the incident power of 0?dBm the divide-by-4 operation range is about 2?GHz (12.3%), from the incident frequency 15.3–17.3?GHz. The divide-by-2 locking range is about 5.1?GHz (77%), from the incident frequency 4.1–9.2?GHz.     

A ring oscillator based frequency synthesizer without using frequency divider

A novel indirect frequency synthesizer (FS) circuit comprising a multiplexer (MUX) controlled ring oscillator (RO) and a Hogge phase detector has been proposed. The circuit will synthesize signals having better spectral purity and will consume less power compared to conventional indirect FS circuits. The MUX controlled RO will provide higher flexibility in frequency control and the voltage controlled oscillator (VCO) sensitivity can be varied easily to keep loop gain fixed for different values of synthesized signal frequencies. Hardware experimental results have been given to establish theoretical anticipations.     

A CMOS oscillator for radiation-hardened,low-power space electronics

This article presents the design, manufacturing and test results of an on-chip CMOS oscillator, using a ring-oscillator, VCO based architecture. The oscillator generates a configurable square waveform clock signal to be used internally or externally to the IC that integrates it, with very low area (320 transistors, 112?×?148?µm) and power overhead (975?µW). The oscillator is integrated in a mixed signal IC which has been qualified for space applications, at a commercial 250?nm process. It enables the standalone operation of the IC without external oscillator and gives the possibility to clock other components and systems. In addition, it reduces the noise interference at PCB and chip level, optimising the performance of sensitive analogue parts. It was validated by radiation tests according to ESA standards’ procedures that the oscillator's functionality and characteristics do not deteriorate with TID levels up to 1Mrad. This approach can be easily adjusted to a wide range of frequencies, while significantly reducing the cost and power budget of space qualified systems with small design effort trade-off.     

Low-power wide-locking-range injection-locked frequency divider for OFDM UWB systems

This paper describes a divide-by-two injection-locked frequency divider (ILFD) for frequency synthesizers as used in multiband orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18 μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz (6.23 to 11.08 GHz) at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38 × 0.28 mm2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.     

Experimental evaluation of hot-carrier stressed series-tuned injection-locked frequency divider

This paper, for the first time, investigates hot carrier effect on a divide-by-2 injection-locked frequency divider (ILFD). The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the series-resonant resonator. It is shown that the locking range decreases and the oscillation frequency increases with stress time, and the phase noise in both the free-running and locked state increases with stress time. The measured operation range after RF stress also shows degradation from the fresh circuit condition.     

适用于OFDM UWB 系统的低功耗，大锁定范围注入锁定分频器

This paper describes a divide-by-two injection-locked frequency divider （ILFD） for frequency synthesizers as used in multiband orthogonal frequency division multiplexing （OFDM） ultra-wideband （UWB） systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz （6.23 to 11.08 GHz） at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38×0.28 mm^2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.     

A low-power direct digital frequency synthesiser

This work presents a low power direct digital frequency synthesiser (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide lookup table ROM into two parts. The ROM size of the proposed architecture is 25% less than that of conventional lookup table DDFS. The hardware of new DDFS architecture compared to the traditional two-level table DDFS also requires less one multiplication. A synthesised 0.35 µm DDFS with an spurious free dynamic range of ?80 dB, runs up to 100 MHz and consumes 81 mW at 3.3 v. The power efficiency is 0.81 mW MHz^?1, which represents an enhancement of more than 38% compared to the conventional DDFS.     

HiperLAN 5.4-GHz low-power CMOS synchronous oscillator

A 5.4-GHz 0.25-μm very-large-scale-integration CMOS synchronous oscillator (SO) is proposed in this paper, which is designed to act as a local oscillator for HiperLAN systems. The advantage of using such an oscillator in a double-loop frequency synthesizer is demonstrated. The design strategy leading to an optimized SO with regards to its synchronization range is described. A test chip is presented, which provides a 150-MHz synchronization range and a -97-dBc/Hz phase noise at 10-kHz offset from the 5-GHz carrier, while consuming only 5 mA from a 2.5-V supply