Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation.The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range(-55 to 150℃).An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism.The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature.The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.     

功率MOS器件在不同温度条件下雪崩特性研究

本文使用实验和二维器件模拟仿真方法研究了高压功率MOS器件在不同温度条件下的耐雪崩能力。实验研究了国产功率MOS器件在最大额定工作温度范围(-55℃～150℃)发生的雪崩能量烧毁行为。采用包含电热非等温模型的ISE TCAD二维仿真软件模拟分析器件发生雪崩失效的机理。无嵌位电感实验数据及模拟结果证明,由于器件内部寄生效应及热效应影响,功率MOS器件雪崩耐量可靠性随着温度升高而退化,其主要原因与雪崩过程引起器件内部寄生双极管开启相关。     

Corrections to "Waveguide Electrooptic Modulators"

Due to typographical errors in the above referenced paper, the following corrections should be made.     

Modeling of the intrinsic retention characteristics of FLOTOXEEPROM cells under elevated temperature conditions

A model for the intrinsic retention characteristics of FLOTOX EEPROM cells is presented, which is based on the temperature dependence of the Fowler-Nordheim emission current. This model which has been successfully tested on single-poly-FLOTOX EEPROM cells, enables the device lifetime to be calculated for given memory operating conditions, instead of being extrapolated as is usually done. The sensitivity of the retention characteristics to several technological parameters is also investigated. It is expected that this intrinsic retention model (with minor modifications) will also be applicable to FLASH EEPROM cells