基于90nm CMOS工艺的60GHz射频接收前端电路设计

设计了一款用于中国60 GHz标准频段的射频接收前端电路。该射频接收前端采用直接变频结构,将59～64 GHz的微波信号下变频至5～10 GHz的中频信号。射频前端包括一个四级低噪声放大器和电流注入式的吉尔伯特单平衡混频器。LNA设计中考虑了ESD的静电释放路径。后仿真表明,射频接收前端的转换增益为13.5～17.5 dB,双边带噪声因子为6.4～7.8 dB,输入1 dB压缩点为-23 dBm。电路在1.2 V电源电压下功耗仅为38.4 mW。该射频接收前端电路采用IBM 90 nm CMOS工艺设计,芯片面积为0.65 mm2。     

A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS

The commercial potential of the 60 GHz band, in combination with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz, for a low area and power consumption of respectively 0.1 ${hbox{mm}}^{2}$ and 65 mW. The presented receiver targets 60 GHz communication where beamforming is required.      

用90nm CMOS数字工艺实现的低抖动时钟锁相环设计

用90nmCMOS数字工艺设计实现了一个低抖动的时钟锁相环.锁相环不需要"模拟"的电阻和电容,采用金属间的寄生电容作为环路滤波器的电容.测试结果显示,锁相环锁定在1.989GHz时的均方抖动为3.7977ps,周期峰峰值抖动为31.225ps,核心功耗约为9mW.锁相环可稳定输出的频率范围为125MHz到2.7GHz.     

用90nm CMOS数字工艺实现的低抖动时钟锁相环设计

用90nmCMOS数字工艺设计实现了一个低抖动的时钟锁相环.锁相环不需要"模拟"的电阻和电容,采用金属间的寄生电容作为环路滤波器的电容.测试结果显示,锁相环锁定在1.989GHz时的均方抖动为3.7977ps,周期峰峰值抖动为31.225ps,核心功耗约为9mW.锁相环可稳定输出的频率范围为125MHz到2.7GHz.     

A Digital Envelope Modulator for a WLAN OFDM Polar Transmitter in 90 nm CMOS

A digital envelope modulator as part of a polar transmitter architecture for the 802.11a/g WLAN OFDM standards is investigated. The digital envelope modulator is quite similar to a state-of-the-art DAC design, but now it has been optimized to deal with envelope signals. A thermometer-coded envelope DAC has been implemented in a 90 nm digital CMOS process. Measurements of a test chip show the digital envelope modulator to reach an OFDM output power of 5 dBm for 54 Mb/s using 64 QAM at 2.45 GHz and fulfilling EVM specifications and in-band spectral mask requirements using just 12.7 mW from a 1.2 V supply. Combining the digital envelope modulator with an off-chip power amplifier gives an output power of 20.4 dBm, while fulfilling EVM specifications and in-band spectral mask requirements. The output power of the presented envelope DAC can be increased in a re-design by scaling device sizes. The envelope DAC is a key component in a software-defined-radio transmitter.     

A 0.1–20 GHz Low-Power Self-Biased Resistive-Feedback LNA in 90 nm Digital CMOS

In this letter, a 0.1–20 GHz low-power low noise amplifier (LNA) is presented. A novel self-biased resistive- feedback topology is proposed. Two inductors inside the feedback loop and a shunt-peaking inductor are exploited to extend the bandwidth. A PMOSFET with inductive degeneration is chosen as the load to boost the gain while maintaining low noise figure (NF) at high frequencies. A source-degeneration inductor is also introduced at the input transistor to ensure good input matching and stability over the entire bandwidth. All inductors are small due to the presence of feedback. The LNA was fabricated using a digital 90 nm CMOS process with 12.7 dB peak power gain, 3.3 dB minimum NF, and ${- 1}~{rm dBm}$ peak input-referred third-order intercept point (IIP3). With 12.6 mW power consumption and 0.12 ${rm mm}^{2}$ active area, this wideband LNA may replace distributed amplifiers (DAs) in many applications.      

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

An 8-phase phase-aligned ring oscillator in 90 nm digital CMOS is presented that operates up to 2 GHz. The low-complexity circuit consumes 13 mW at 2 GHz and 1.2 mW at 400 MHz, while a flat in-band phase noise below $-$120 dBc$/$Hz is achieved, in close agreement with the presented theory. The circuit occupies an area of 0.008 mm$^{2}$ .      

A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications

A CMOS-compatible gate-controlled lateral BJT (GC-LBJT) was prepared with a conventional 90 nm CMOS technology for radio frequency system-on-chip (RF SoC) applications. The emitter injection efficiency and the doping profile in P-well were optimized by properly controlling source, drain, and well implants. Consequently, the GC-LBJT with a gate length of 0.15 μm can achieve a current gain over 2000 and 17/19 GHz for the f_T/f_max, respectively, which are 1000%, 200%, and 60% improvements in current gain, f_T and f_max, respectively as compared to the LBJT reported previously.     

Integrating thick copper/Black Diamond™ layer in CMOS interconnect process for RF passive components

Thick copper (Cu)/Black Diamond™ (BD) layer up to 4 μm has successfully been integrated in CMOS interconnect process to improve the quality of on-chip RF passive components. It is shown that BD film is easy to crack when its thickness is up to 4 μm. However, by inserting one or few layers of dielectric material, BloK™, the stress in the entire dielectric film stack can be reduced. Although the reduction of the tensile stress of the stack is insignificant, the inserted BloK™ layer effectively prevents cracking from happening in the film stack. Spiral inductors have been integrated in developed Cu/BD (4 μm) top-metal-layer. Both Q value and resonate frequency of developed inductors are improved comparing to the inductors fabricated in previous top-metal-layer with 1 μm Cu/SiO₂ stack.     

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of$-$110 dBm at 60mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates.     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

A broadband RF 65 nm CMOS front-end for cable TV reception

A novel broadband RF front-end in 65 nm CMOS technology is presented. The front-end serves to precondition the incoming RF spectrum for further processing in a cable TV receiver architecture where RF channel selection and down conversion are done in digital domain. The analog front-end consists of a broadband highly linear low-noise amplifier followed by a variable gain RF amplifier. An original broadband circuit topology for the amplifiers is adopted.The fabricated front-end exhibits a bandwidth of 50-1050 MHz, a variable gain, which spans from 12 to 37 dB with a 0.2 dB step, an OIP3 of 28.4 dBm (77.5 dBmV), an OIP2 of 65 dBm (114 dBmV), and a noise figure of 5.8 dB, dissipating 125 mW at 1.2 V supply, and a core silicon area of 0.4 mm².     

Implementation of plug-and-play ESD protection in 5.5 GHz 90 nm RF CMOS LNAs—Concepts, constraints and solutions

Design and implementation of ESD protection for a 5.5 GHz low noise amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as “plug-and-play”, is used as ESD protection for the RF pins. The consequences of design and process, as well as, the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail. Enhancement in the ESD robustness using additional core-clamp diodes is proposed.     

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs

Design automation tools have been developed to suppress CDE-induced latchup in CMOS ASICs. The tools govern the placement of I/Os and cores subject to CDE and automate the insertion of well and substrate contacts with varying periodicities around CDE susceptible cells according to rules derived from an analytical latchup model.     

IF Amplifier Section in 90 nm CMOS Technology for SoC Microwave Radiometers

In this letter a novel design solution in 90 nm CMOS technology is proposed for the IF amplifier, low-pass filter and square-law power detector of a system-on-chip (SoC) microwave radiometer. To minimize the number of off-chip components (just a single capacitor) the IF filter is based on an active $g_{m}C$ configuration, whereas the power detector exploits the MOS transistor non-linearity, i.e., avoiding the need for Schottky diodes. The fabricated IF chip features a sensitivity of 3 mV/nW, a linearity range of about 25 dB around the $-$60 dBm level, a noise equivalent bandwidth of 58 MHz and a current consumption of only 1.8 mA at 1.2 V supply. The core area is within a rectangle of $220 mu{rm m}times 540 mu{rm m}$. The proposed design solution is also compatible with SiGe BiCMOS processes and can be regarded as a further step toward the realization of microwave radiometric sensors fully integrated on silicon.      

一种应用于GNSS接收机的无电感多模射频前端

本文设计了一种应用于GNSS接收机的无电感多模射频前端。与传统低噪声放大器结构不同,本设计使用了无电感电流模式以及利用噪声消除技术的低噪声放大器。其高阻输入的射频放大器进一步放大信号并将单端信号转为差分信号。后级无源混频器将信号下变频到中频并将信号传输到下一级的模拟电路模块。文中还有本振缓冲器实现压控振荡器的二分频和25%占空比的方波新号的产生用于控制混频器开关。测试结果表明该射频前端在1.2V电源电压下仅消耗6.7mA电流,并获得了良好的综合性能。射频前端的输入回损为-26dB,而1.43dB的低噪声系数也保证了良好的接收灵敏度。在射频前端电压增益为48dB情况下,测得的输入1dB压缩点为-43dBm。该电路采用了55nm标准CMOS工艺实现,面积非常小,仅仅为220 μm×280 μm左右。     

A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS

A 5 bit 1.75 GS/s ADC using a factor 2 dynamic folding technique is presented. The 2X folding lowers the number of comparators from 31 to 16, simplifies encoding and reduces power consumption and area. The comparators in this converter are implemented with built-in references and calibration to further reduce power consumption. INL and DNL after calibration are smaller than 0.3 LSB, with an SNDR of 29.9 dB at low frequencies, and above 27.5 dB up to the Nyquist frequency. The converter consumes 2.2 mW from a 1 V supply, yielding a FoM of 50 fJ per conversion step and occupies 0.02 ${hbox{mm}}^{2}$ in a 90 nm 1P9M digital CMOS process.      

软件无线电中的数字化快速解调算法

软件无线电中信号的调制与解调是研究的重点问题之一。文章基于希尔伯特变换提出了一种在软件无线电中的数字化快速解调算法，理论分析和仿真结果表明，该解调方案的抗干扰性能有明显改善，与传统解调方法相比，通用性强、简单、计算量小且易于实现，能很好地满足软件无线电中的要求。具有理论意义和实际应用价值．     

High linearity,low power RF mixer design in 65 nm CMOS technology

A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB.