一种高精度CMOS微弱电流读出电路

本文介绍了一种高精度CMOS微弱电流读出电路。该电路能够将十分微弱的电流信号精确地转化为频率信号以用于电流的测量,并将结果转化为10位数字信号输出。本设计提出了一种快速的稳定增强型恒电位仪,该恒电位仪能为安培型生化传感器提供恒定的偏置电压。电路中还采用了源极电压转移技术,在室温条件下,该技术能使MOS管的漏电流降低到反向偏置二极管的漏电流水平,大大提高了电流检测的精度。该芯片采用了新加坡特许半导体公司0.35μm标准CMOS工艺,电源电压3.3V。该读出电路具有超过100dB的大动态范围,能够精确地检测出从1pA到300nA的电流,且全量程范围内非线性误差不超过0.3%。     

A high precision CMOS weak current readout circuit

rents from 1 pA to 300 nA can be detected with a maximum nonlinearity of 0.3% over the full scale.     

红外焦平面CMOS单元读出电路

研制出一种 Ｃ Ｍ Ｏ Ｓ 差分放大器组成的电容反馈互导放大器（ Ｃ Ｔ Ｉ Ａ） 型红外焦平面读出电路,其输出端带有相关双取样（ Ｃ Ｄ Ｓ） 电路。对读出电路的注入效率进行了计算机模拟。介绍了器件的设计与工艺分析。实验结果表明,在７７ Ｋ 下,读出电路的动态范围为６６ ｄ Ｂ,功耗典型值为０ ．５３ 毫瓦／ 位     

CMOS circuit for readout of microbolometer arrays

A CMOS circuit for the readout of microbolometer arrays is presented. It provides a pulsed bias for the microbolometers, signal amplification and multiplexing to a common output. The chip can be used with linear and small two-dimensional arrays of microbolometers realising a hybrid infrared sensor     

Time-constant-based CMOS readout circuit for DNA detection

An RC-to-time constant interface circuit was implemented in 0.18 mum CMOS to characterise the conductive polymer labelled deoxyribonucleic acid (DNA) hybridisation activity on nano-sensor micro-arrays. Measured results show that sub-picomolar DNA (0.1-10 pM) are able to be differentiated with respect to their electrical parameters of 1-23 GOmega resistances parallel with 2.8 down to 0.1 nF capacitances.     

Column readout circuit with global charge amplifier for CMOS APSimagers

A CDS readout circuit for CMOS active pixel sensor (APS) imagers is presented. The proposed CDS circuit is simple, requires only one output amplifier, and is based on capacitor ratios, reducing the column fixed pattern noise     

微光CMOS图像传感器读出电路研究

高性能的信号读出电路是微光CMOS图像传感器的重要组成部分,如何降低读出电路噪声,提高读出电路输出信号的信噪比成为读出电路设计的重点。本文设计了一种高增益低噪声的电容反馈跨阻放大器CTIA（Capacitive Trans impedanceAmplifier）与相关双采样电路CDS （Correlated Double Sampling）相结合的微光探测器读出电路。在CTIA电路中,采用T网络电容实现fF级的积分电容,并通过增益开关控制,来达到对微弱光信号的高增益低噪声读出。采用CSMC公司的0.5μm标准CMOS工艺库对电路进行流片,测试结果表明：在光电流信号为20~300 pA范围内,积分时间为20μs,该电路功能良好,信噪比（SNR）达到10,能应用于微光CMOS图像传感器。     

Precise FPN compensation circuit for CMOS APS [imager]

Fixed pattern noise (FPN) is one of the major disadvantages of CMOS imagers in comparison with CCD imagers. A simple and precise FPN compensation circuit for a CMOS active pixel sensor (APS) imager with an in-line non-destructive readout function is presented     

A PtSi Schottky-barrier area imager with meander-channel CCD readout registers

This paper describes improvement of the fill factor of Schottky-barrier infrared CCD arrays by using a meander-channel CCD (MCCD) as both the vertical and the horizontal readout registers. A 64 × 64 element monolithic Schottky-barrier infrared meander channel CCD(SB-IRMCCD) with 23 percent fill factor has been fabricated with negligible element to element cross talk. This letter also describes how a fill factor of 57 percent is possible by decreasing the area of the vertical MCCD register to 30 percent of that in the present device.     

一种用于MEMS电容式加速度计的116dB动态范围CMOS读出电路

A high stability in-circuit reprogrammable technique control system for a capacitive MEMS accelerometer is presented. Modulation and demodulation are used to separate the signal from the low frequency noise. A low-noise low-offset charge integrator is employed in this circuit to implement a capacitance-to-voltage converter and minimize the noise and offset. The application-specific integrated circuit （ASIC） is fabricated in a 0.5 /μm one-ploy three-metal CMOS process. The measured results of the proposed circuit show that the noise floor of the ASIC is -116 dBV, the sensitivity of the accelerometer is 66 mV/g with a nonlinearity of 0.5%. The chip occupies 3.5×2.5 mm2 and the current is 3.5 mA.     

CMOS readout circuit allowing microbolometer arrays to operate without temperature stabilisation

A new CMOS readout circuit that controls the non-uniformity of microbolometer arrays as a function of operating temperature change is described. This circuit provides a nonlinear bias current for operating temperature using a MOS transistor that is operated in the subthreshold region. This approach allows microbolometer arrays to operate without temperature stabilisation up to an operating temperature change of approximately 40K.     

CMOS TDI readout circuit that improves SNR for satellite IR applications

A novel CMOS readout circuit for a satellite infrared time delay and integration (TDI) array is proposed. An integrate-while-read readout for the TDI scheme is adopted, and a dead pixel elimination circuit solving a critical problem of the TDI scheme is integrated within a chip. In addition, an adaptive charge capacity control method is utilised to improve the signal-to-noise ratio (SNR). Using the proposed circuit, the SNR at 200 K can be improved by as much as 12 dB.     

A CMOS uncooled heat-balancing infrared imager

In this paper, we report the fabrication, design, and testing of an uncooled 8×8 infrared imager based on an active pixel heat balancing technique. The imager is fabricated using a commercial CMOS process plus a simple electrochemical etch stop releasing step. The basic active pixel detector structure consists of a simple cascode CMOS amplifier in which the PMOS devices are built inside a thermally isolated floating n-well. The intrinsic coupling of the cascode currents with the self-heating of the well forms an electrothermal feedback loop that tends to maintain the well temperature constant, By employing the heat balance between incoming infrared radiation and the PMOS device power dissipation, the responsivity of the detector is controlled by the cascode biasing current. Measurements show responsivities between 0.3-1.2×10⁶ V/W when the infrared source is chopped at 20 Hz and a detectivity D*=3×10⁷ cm√(Hz)W^-1 at 30 Hz. Noise measurements suggest that a D* of 10⁸ cm√(Hz)W^-1 is achievable in this design     

Column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor

High linearity and low noise column readout chain are two key factors in CMOS image sensor. However, offset mismatch and charge sharing always exist in the conventional column wise readout implementation, even adopting the technology of correlated double sample. A simple column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor is proposed in this paper. Based on the bottom plate sampling and fixed common level method, this novel design can avoid the offset nonuniformity between the two buffers. Also, the single buffer and switched capacitor technique can effectively suppress the charge sharing caused by the varied operating point. The proposed approach is experimentally verified in a 1024 × 1024 prototype chip designed and fabricated in 55 nm low power CMOS process. The measurement results show that the linear range is extended by 20%, the readout noise of bright and dark fields is reduced by 40% and 30% respectively, and the improved photo response nonuniformity is up to 1.16%. Finally, a raw sample image taken by the prototype sensor shows the excellent practical performance.     

基于自偏置电流镜的CMOS红外焦平面读出电路

针对高精度红外焦平面阵列应用设计了一种具有高注入效率、大动态范围、稳定的探测器偏压、小面积和低功耗的自偏置电流镜注入CMOS读出电路.所设计的电路结构包括一种由自偏置的宽摆幅PMOS共源共栅电流镜和NMOS电流镜构成的反馈结构读出单元电路和相关双采样电路.对所设计电路采用Chartered 0.35 μm CMOS工艺进行了流片.测试结果显示:电路线性度达到了99%,探测器两端偏压小于1mV.电路输入阻抗近似为0,单元电路面积为10μm×15μm,功耗小于0.4μW.电量存储能力3108电子.测试结果表明:电路功能和性能都达到了设计要求.     

New CMOS readout circuit with background suppression and CDS for infrared focal plane array applications

A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm× 15 μm area and consumes less than 0.4 mW power. Charge storage...     

A CMOS readout amplifier for instrumentation applications

An integrated readout amplifier for instrumentation applications in smart sensor systems is presented. A fully integrated CMOS version of such an amplifier has been developed using switched-capacitor techniques. The amplifier system provides differential input capability, programmable amplification, clock generation, and low-pass filtering on the chip. The output signal is continuous in time and the system can be used without any of the special precautions necessary for sampled-data circuits. Emphasis was put on high PSRR (-63 dB at DC), low noise (10-μV_rms input equivalent wideband noise) and offset, low harmonic distortion, and small amplification error (<0.06% at 4 V_pp). To cover a large field of applications, only slightly different realizations can be used for capacitive sensors as well as for resistive sensor bridges     

New dark current suppression CMOS readout circuit with novel CDS structure for large format QWIP FPA

A new Dark Current Suppression (DCS) CMOS readout circuits for large format Quantum-Well-Infrared Photo-detector (QWIP) Focal-Plane-Array (FPA) with novel CorrelatedDouble-Sampling (CDS) structure based on dynamic source-follower are proposed, which can overcome the drawbacks of the present techniques, such as sensitive to the non-uniformity of the QWIP materials, poor readout noise features, low frame frequency, limited injection efficiency and dynamic range, etc. The dummy is adopted to realize dark current suppression, while the cascode current mirror (with current ratio of 1:10) can increase charge sensitivity and reduce integration time. Through the novel CDS structure, the output waveform is boxcar, and the frame frequency is increased. Simulation results demonstrate that, in high background sense, the proposed DCS circuit can suppress the dark current, achieve good readout performance, such as low power consumption, high charge sensitivity, high resolution, large dynamic range, and insensitive to the non-uniformity of the QWIP materials.     

Trimming CMOS smart imager with tunnel-effect nonvolatile analogue memory

Amplified MOS imagers (AMIs) have the advantage of being compatible with conventional CMOS analogue/digital circuit design. One of the major problems in AMIS is their large fixed pattern noise compared to CCD imagers. The Letter presents the structure of a nonvolatile tunnel-effect analogue memory which is fully compatible with a standard CMOS process and which can reduce significantly the offset-like fixed pattern noise in AMI arrays.<>     

An enhanced-performance CMOS imager with a flushed-reset photodiode pixel

A new front-end for photodiode-based CMOS imagers is presented. Degradation in imaging performance due to conventional hard- and soft-reset of pixels is analyzed. To overcome these limitations, the design and operation of a flushed-reset pixel is described. The flushed-reset pixel combines the best of hard- and soft-reset to simultaneously provide excellent radiometric accuracy, high linearity, no image lag, high saturation level, and reduced read-noise. The new front-end is implemented by changes to the column-circuitry only, leaving the pixel unchanged, preventing degradation of any unrelated imaging performance. It is compatible with large format imager implementation, has minimal impact on the frame-rate, and does not introduce any additional hot-carrier stress in the pixel. Data from a large format (512/sup 2/) imager demonstrates the efficacy of the flushed-reset pixel approach.