集成铁电存储器——新型快速,抗辐照,非挥发性存储器件

本文介绍了铁电存储器的原理，对非挥发性铁电存储的研究和开发情况作了综述。并就制约着铁电集成器件真正商业化的若干铁电薄膜材料物理方面关键问题作了分析。首先提出了在铁电集成器件工艺中还存在着综合优化问题。最后，对铁电存储器的未来作了预测。     

纳米晶非挥发性存储器研究进展

介绍了纳米晶非挥发性存储器的发展状况和基本工作原理,比较了纳米晶非挥发性存储器所涉及到的各种不同的电荷输运机制,系统介绍了纳米晶非挥发性存储器在纳米晶材料设计、纳米晶晶体生长控制方法、隧穿/控制介质层工程和新型存储器器件结构等方面的一些最新研究进展,对纳米晶非挥发性存储器的研究趋势进行了展望。     

N2O气氛退火对SONOS非易失性存储器性能的优化研究

SONOS(Silicon-Oxide-Nitride-Oxide-Silicon)型非易失性存储器件的电荷保持能力与Si-SiO2界面态的质量密切相关.通过在SONOS的隧穿氧化层工艺流程中增加适当的N2O退火工艺,改善了器件的擦除深度和编程速度,从而使得SONOS器件的存储器性能得到优化.通过进一步电荷泵测试表明,...     

SONOS非易失性存储器件研究进展

随着半导体存储器件的小型化、微型化,传统多晶硅浮栅存储因为叠层厚度过大,对隧穿氧化层绝缘性要求过高而难以适应未来存储器的发展要求。最近,基于绝缘性能优异的氮化硅的SONOS非易失性存储器件,以其相对于传统多晶硅浮栅存储器更强的电荷存储能力、易于实现小型化和工艺简单等特性而重新受到重视。文章论述了SONOS非易失性存储器件的存储原理和存储性能的影响因素研究进展,并在材料、工艺与结构设计等方面对SONOS存储器件性能改进的研究进展情况进行了分析和讨论。     

阻变存储器及其集成技术研究进展

在各种新型非挥发性存储器中,阻变存储器(RRAM)具有成为下一代存储器的潜力.介绍了RRAM器件的基本结构,分类总结了常用的材料以及制备工艺,对RRAM阵列的集成方案进行了比较,并讨论了目前存在的问题;最后,对RRAM的研究趋势进行了展望.     

有机非挥发存储器件:浮栅结构有机薄膜晶体管

提出了一种浮栅结构的新型有机薄膜晶体管(FG-OTFT)器件,并阐述了这种器件的工作机理.该器件通过控制浮 置栅上的电荷来控制 FG-OTFT 器件的阈值电压的大小,而器件不同的阈值电压便可用来存储“0”和“1”两个状态,故这种器 件可以被用作有机非挥发存储器.我们通过计算机数值模拟的方法对这种器件进行了研究.研究表明...     

利用改进的电荷泵法研究SONOS存储器陷阱电荷的分布特性

在silicon-oxide-nitride-oxide-silicon(SONOS)等电荷俘获型不挥发存储器中,编程操作后注入电荷的分布会对器件的读取、擦写以及可靠性带来影响.利用电荷泵方法可以有效而准确地测量出注入电荷沿沟道方向的分布.为了提高测试精度,在进行电荷泵测试时,采用固定低电平与固定高电平相结合的方法,分别对SONOS器件源端和漏端进行注入电荷分布的测试.通过测试,最终获得SONOS存储器在沟道热电子注入编程后的电子分布.电子分布的峰值区域在漏端附近,分布宽度在50nm左右.     

嵌入式相变存储器的技术特点和研究现状

从2001年Intel在IEDM发表第一篇相变存储器的论文以来,相变存储器的发展十分迅猛.相变存储器由于具有非易失性、循环寿命长、元件尺寸小、功耗低、可多级存储、高速读取、抗辐射、耐高低温、抗振动、抗电子干扰和制造工艺简单等优点,被认为最有可能取代目前的FLASH和DRAM而成为未来半导体存储器主流产品.文中系统地介绍了嵌入式相变存储器的存储机理及其主要工作特点,从相变材料,器件结构,存储阵列等方面分析国内外研究现状,并讨论了器件失效与可靠性问题.     

利用改进的电荷泵法研究SONOS存储器陷阱电荷的分布特性

在silicon-oxide-nitride-oxide-silicon(SONOS)等电荷俘获型不挥发存储器中,编程操作后注入电荷的分布会对器件的读取、擦写以及可靠性带来影响.利用电荷泵方法可以有效而准确地测量出注入电荷沿沟道方向的分布.为了提高测试精度,在进行电荷泵测试时,采用固定低电平与固定高电平相结合的方法,分别对SONOS器件源端和漏端进行注入电荷分布的测试.通过测试,最终获得SONOS存储器在沟道热电子注入编程后的电子分布.电子分布的峰值区域在漏端附近,分布宽度在50nm左右.     

高k介质在浮栅型非挥发性存储器中的应用

随着微电子技术节点不断向前推进,基于传统浮栅结构的非挥发性存储器(NVM)技术遇到严重的技术难点,其中最主要的问题是SiO2隧穿层已经接近厚度极限,很难继续减薄.作为改进措施,引入高k介质作为新型隧穿层材料.文章介绍了高k材料的研究现状和在NVM器件中应用所取得的进展;最后,对高k介质进一步应用的研究趋势进行了展望.     

Polycrystalline Si Nanowire SONOS Nonvolatile Memory Cell Fabricated on a Gate-All-Around (GAA) Channel Architecture

In this letter, we present SONOS nonvolatile memory device with gate-all-around polycrystalline silicon (poly-Si) nanowire channel. The SONOS memory cell with 23-nm nanowire width, fabricated using top-down CMOS process, exhibits fast programming and erasing speed as well as improved subthreshold behavior of the transistor. Both the memory and transistor characteristics are dependent on the nanowire width—smaller the width, better the performance. The good device characteristics along with simple fabrication method make the poly-Si nanowire SONOS memory a promising candidate for future system-on-panel and system-on-chip applications.      

A low voltage SANOS nonvolatile semiconductor memory (NVSM) device

In this paper, we present a new Polysilicon–Aluminum Oxide–Nitride–Oxide–Silicon (SANOS) device structure suitable for future nonvolatile semiconductor memories. Replacing SiO₂ with a high-K material, Al₂O₃ (K_f = 9) as the top blocking layer of the conventional SONOS device increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer with its dielectric constant during write and erase operations. Therefore, this new device can achieve lower programming voltages and faster programming speed than the conventional SONOS device. We have fabricated SANOS capacitors with 2 nm tunnel oxide, 5 nm silicon nitride and 8 nm aluminum oxide and studied the programming speed and charge retention characteristics of the new devices. These new SANOS devices achieve a 2 V reduction in the programming voltages with 2.1 V initial memory window.     

A new SONOS memory using source-side injection for programming

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications     

On the go with SONOS

Advancements in scaling gate insulators for MOS transistors permit low-voltage, silicon-oxide-nitride-silicon (SONOS) nonvolatile semiconductor memories (NVSMs) for a wide range of applications. The continued scaling of SONOS devices offers improved performance with a small cell size, single-level polysilicon with low voltage, fast erase/write, improved memory retention, increased endurance, and radiation hardness. In this article, we discuss scaled SONOS devices, SONOS memory technology, and some SONOS NVSM applications     

Effects of two-step high temperature deuterium anneals on SONOSnonvolatile memory devices

The deterioration of the Si-SiO₂ interface is associated with the degradation of long-term retention in polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memory (NVSM) devices. Two-step high temperature deuterium anneals, applied in SONGS device fabrication for the first time, improves the endurance characteristics and retention reliability over traditional hydrogen anneals. Electrical characterization shows deuterium-annealed SONOS devices have nearly one order of magnitude longer retention time than hydrogen-annealed devices after 10⁷ erase/write cycles at 85°C to provide an extrapolated 0.5 V detection window at ten years     

A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory

In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V_th) , and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.     

Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device

This letter studies the nonvolatile memory characteristics of polycrystalline-silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant trap-assisted gate-induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which lies above the gate-to-drain overlap region. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection into the nitride layer. Because the injected hot holes can remain in the nitride layer after repeated Fowler–Nordheim erase and program operations, this method can exhibit good sustainability in such a SONOS-TFT memory device.      

Novel SONOS – type nonvolatile memory device with stacked tunneling and charge trapping layers

Operation properties of polysilicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile semiconductor memory (NVM) devices with stacked tunneling and charge trapping layers were investigated in this work. Clear enhancement on operation speed and satisfactory retention of NVM device were achieved by adopting stacked tunneling oxide. Enhancement on programming speed but degradation on erasing operation was observed for device with stacked charge trapping layer. Finally, operating characteristics of devices with stacked tunneling oxide, stacked charge trapping layer, and combining both stacked tunneling oxide and charge trapping layer were compared and discussed.     

Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory fabricated by a simple sidewall spacer formation

A novel omega-shaped-gated (Ω-Gate) poly-Si thin-film-transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices fabricated with a simple process have been proposed for the first time. The Ω-Gate structure inherently covered two sharp corners manufactured simply via a sidewall spacer formation. Due to the sharp corner geometry, the local electric fields across the tunneling oxide could be enhanced effectively, thus improving the memory performance. Based on this field enhanced scheme, the Ω-Gate TFT SONOS revealed excellent program/erase (P/E) efficiency and larger memory window as compared to the conventional planar (CP) counterparts. In addition, owing to the better gate controllability, the Ω-Gate TFT SONOS also exhibited superior transistor performance with a much higher on-current, smaller threshold voltage, and steeper subthreshold swing. Therefore, such an Ω-Gate TFT SONOS memory is very promising for the embedded flash on the system-on-panel applications.