Hybrid picture coding with wavelet transform and overlappedmotion-compensated interframe prediction coding

A novel video coding scheme using an orthonormal wavelet transform is proposed. The wavelet transform is used in a motion compensated interframe coder in which a blockless motion compensation technique is employed to increase efficiency of wavelet transform coding. A new scanning method for wavelet coefficients is also proposed which is rather different from subband coding. Simulation work is carried out to evaluate the proposed coding method. Significant improvement in subjective quality is obtained over that obtained with conventional hybrid coding methods that use blockwise motion compensation and DCT. Some improvement has also been realized in the signal to noise ratio. Although wavelet coding is still in its early stages of development, it appears to hold great promise for motion picture coding     

A novel method for fault diagnosis of analog circuits based on WP and GPNN

A novel method for fault diagnosis of analog circuits with tolerance based on wavelet packet (WP) decomposition and probabilistic neural networks using genetic algorithm (GPNN) is proposed in this paper. The fault feature vectors are extracted after feasible domains on the basis of WP decomposition of responses of a circuit being solved. Then by fusing various uncertain factors into probabilistic operations, GPNN methods to diagnose faults are proposed whose parameters and structure obtained form genetic optimisations resulting in best detection of faults. Finally, simulations indicated that GPNN classifiers are correct 7% more than BPNN of the test data associated with our sample circuits.     

Analog Implementation of Wavelet Transform in Switched-Current Circuits with High Approximation Precision and Minimum Circuit Coefficients

This paper presents a novel procedure for analog implementation of wavelet transform in switched-current (SI) circuits. An improved hybrid PSO–SQP optimization is employed to precisely approximate the impulse response of a filter to the wavelet base function in time domain. The SI first- and second-order section circuits with minimum coefficients are designed based on infinite-impulse-response digital filter technology. Cascode techniques are occupied to reduce the effects of parasitic elements. Based on these SI first- and second-order section circuits, a parallel wavelet circuit structure is presented to synthesize the approximated wavelet base function. By adjusting the switch clock frequency, the wavelets at different scales can be realized. The Gaussian wavelet is selected as an example to illustrate the design procedure. Simulation results demonstrate the feasibility of the proposed procedure for analog wavelet transform in SI circuits.     

基于小波平衡的非线性电路稳态模拟

本文提出一种基于小波理论的非线性电路稳态模拟算法――小波平衡法.该方法在时域中求解电路稳态响应,克服了频域模拟算法由于谐波次数较高导致计算量很大的缺点,具有复杂度低,精度高,存在一个自适应算法自动选择模拟阶数等优点.模拟结果证明,本文的小波平衡法是一种十分有效的方法.     

非线性自动压扩的开关电流电路行为级建模方法

提出了一种新的基于非线性压扩函数自动构造的开关电流电路行为级建模方法,从而简化电路的建模和仿真.与原有的建模方法相比,该方法不仅可以对模型的误差分布进行有效地调控,而且能够降低模型的误差.为了验证本文所提出的行为级建模方法,对几种开关电流电路进行了建模和模拟试验.     

非线性自动压扩的开关电流电路行为级建模方法

提出了一种新的基于非线性压扩函数自动构造的开关电流电路行为级建模方法,从而简化电路的建模和仿真.与原有的建模方法相比,该方法不仅可以对模型的误差分布进行有效地调控,而且能够降低模型的误差.为了验证本文所提出的行为级建模方法,对几种开关电流电路进行了建模和模拟试验.     

Low-power Analog VLSI Implementation of Wavelet Transform

For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.     

基于CMOS对数域积分器的小波变换模拟VLSI实现

提出了一种基于CMOS对数域积分器的连续Marr小波变换模拟VLSI实现方法.构造了Marr母小波时域逼近函数模型,用Levenbery-Marquardt非线性最小二乘法求解模型参数最优解,得到母小波逼近函数.设计了以CMOS对数域积分器为积木块的小波变换电路,该电路由冲激响应为母小波逼近函数及其伸缩函数的滤波器组构成,滤波器组采用低灵敏度的IFLF结构进行综合.SPICE仿真结果表明该方法的可行性.     

Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece‐wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.     

Analog VLSI implementation of wavelet transform using switched-current circuits

For applications requiring low-voltage low-power and real-time processing, a novel scheme for the VLSI implementation of wavelet transform (WT) using switched-current (SI) circuits is presented. SI circuits are well suited for these applications since the dilation constant across different scales of the transform can be implemented, and controlled by both the aspect-ratio of the transistors and the clock frequency. The quality of such implementation depends on the accuracy of the corresponding wavelet approximation. First, an optimized procedure based on differential evolution algorithm (DE) is applied to approximate the transfer function of a linear steady-state system whose impulse response is the required wavelet. The proposed approach significantly improves the accuracy of approximation wavelets. Next, the approximation of time-domain wavelet function is implemented by the SI analog filters. Finally, the design of the complete SI filter based on first-order and biquad section as main building block is detailed. Simulations demonstrate the performance of the proposed approach to analog WT implementation.     

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology     

模拟大规模电路的快速频域小波配置法

提出了一种求解状态方程的方法:频域快速小波配置法.通过将状态方程转入频域求解,并对输出变量直接进行小波展开.这一方法比原有的时域快速小波配置法大大减少了未知变量的数目,从而使计算速度和存储空间都有很大程度的改善.由于小波函数及其反变换均有显式的数学表达式,这一方法在得到频域解析近似解的同时就可以获得时域解析近似解,无须在计算过程中进行耗时的数值积分反变换.同时通过自适应算法的引入,这一方法可以有效提高计算效率.     

A Novel Method for the Diagnosis of the Incipient Faults in Analog Circuits Based on LDA and HMM

Diagnosis of incipient faults for electronic systems, especially for analog circuits, is very important, yet very difficult. The methods reported in the literature are only effective on hard faults, i.e., short-circuit or open-circuit of the components. For a soft fault, the fault can only be diagnosed under the occurrence of large variation of component parameters. In this paper, a novel method based on linear discriminant analysis (LDA) and hidden Markov model (HMM) is proposed for the diagnosis of incipient faults in analog circuits. Numerical simulations show that the proposed method can significantly improve the recognition performance. First, to include more fault information, three kinds of original feature vectors, i.e., voltage, autoregression-moving average (ARMA), and wavelet, are extracted from the analog circuits. Subsequently, LDA is used to reduce the dimensions of the original feature vectors and remove their redundancy, and thus, the processed feature vectors are obtained. The LDA is further used to project three kinds of the processed feature vectors together, to obtain the hybrid feature vectors. Finally, the hybrid feature vectors are used to form the observation sequences, which are sent to HMM to accomplish the diagnosis of the incipient faults. The performance of the proposed method is tested, and it indicates that the method has better recognition capability than the popularly used backpropagation (BP) network.     

Design of low distortion active inductor and its applications

This paper proposes a novel distortion reduction technique for active inductors. A bias current of a MOSFET, which acts as transconductor in an active inductor, is controlled to reduce a distortion of a active inductor. When an input voltage increases, the bias current is decreased by a control circuit. As a result of this control, transconductance of the MOSFET remains constant. An active inductor using this technique is free from distortion caused by a transconductance variation of a MOSFET. The proposed technique is applied to two different conventional active inductors and novel low distortion active inductors are derived. Computer simulations show that distortion of the proposed active inductor is very low. The proposed low distortion active inductors are applied to a second order bandpass filter and a voltage controlled oscillator. Thanks to the proposed technique, distortion of these circuits are reduced and their performance is improved.     

基于小波分析和神经网络的模拟电路故障诊断方法

提出了一种基于神经网络和小波分析的模拟电路故障诊断的系统方法。该方法通过对电路的可测性测度计算，选择电路的最佳测试节点，然后利用小波分析作为特征提取手段提取电路的故障特征向量，经归一化和主元分析（PCA）处理后。得到最优特征向量，最后输入到神经网络实现电路故障诊断。计算机仿真结果表明该方法具有更好的故障分辨率。     

A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis

Research work done has shown that power consumption in digital integrated circuits can be effectively reduced by reducing the switching activity occurring on the functional modules. High-level synthesis of digital integrated circuits for low power often optimizes the switching activity during the two main synthesis processes, operation scheduling and module binding, which are usually performed one control step at a time in two separated stages. As the two processes are strongly interdependent, separate optimization of switching activity in a step-by-step manner frequently leads to sub-optimal solutions. In this paper, we propose a novel look-ahead synthesis technique with backtracking for the reduction of switching activity in low power high-level synthesis, which not only performs the scheduling and binding simultaneously in an integrated manner using a weighted bipartite technique, but also employs a branch and bound approach with look-ahead evaluation of switching activity for one or more control steps. The look-ahead technique generates multiple schedulings and bindings at the same time in one control step and uses each of them to generate more schedulings and bindings for the next one or more control steps. The best scheduling and binding pattern is then used for backtracking, therefore, effectively reducing the probability for the solutions to fall into local minimum. We tested the look-ahead algorithm with several published benchmarks and the experimental results obtained show that the switching activity can be reduced significantly, with an average of more than 50% reduction in switching activity for the tested benchmarks.     

Induction machine fault diagnostic analysis with wavelet technique

A wavelet transform based method was developed for diagnosing machine faults operating at different rotating speeds. This paper shows that machine fault diagnosis can be effectively performed when an appropriate narrow-band filter is used to extract the required spectra components. A wavelets-transform-based technique is used to design specified narrow filter banks. This enables effective machine fault diagnostic analysis to be performed in the frequency domain. Gaussian-enveloped oscillation-type wavelet is employed. By matching the wavelet basis functions with the associated faulty signals, the required narrow filter banks are obtained. As a result, the detection and diagnosis of machine faults operating at different rotating speeds are made possible. The proposed technique was thoroughly tested at different rotating speeds.     

基于新型极性转换技术的XNOR/OR电路面积优化

极性转换是Reed-Muller(RM)逻辑电路优化的基本环节,该操作的具体数量随电路规模增长而增加,其速度直接影响整体优化算法的效率。针对RM电路的XNOR/OR实现形式,推导电路面积优化的数学模型;结合当前极性转换算法的优势,提出一种新型极性转换技术;根据新型极性转换的特点,构建适用于较大规模XNOR/OR电路的面积优化算法。实验结果表明,与已有极性转换方法相比,所提新型极性转换技术能明显改善XNOR/OR电路面积优化的效率。     

连续小波变换开关电流电路的实现

提出了一种用开关电流电路实现连续小波变换的方法,将连续小波变换转化为用带通滤波器组对信号进行处理,并用开关电流电路实现该带通滤波器组.文章采用基于第二代开关电流技术的带通滤波器组实现了8通道的Marr小波.仿真结果表明该滤波器组具有恒Q值,且每个带通滤波器的中心频率与理论值大致相符,从而证实了该方法的可行性.     

Gallium arsenide heterojunction transistor integrated circuits for a limiting amplifier and synchronizer

Design of gallium arsenide heterojunction transistor integrated circuits for a limiting amplifier and synchronizer is considered. A novel circuitry of amplifying stages is proposed. Computer simulation is performed. Devices capable of 12.5-Gbps data transmission speed are investigated experimentally. Good agreement of experimental and simulation results is obtained.