Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata

Quantum Cellular Automata (QCA) is a novel and attractive method which enables designing and implementing high-performance and low-power consumption digital circuits at nano-scale. Since memory is one of the most applicable basic units in digital circuits, having a fast and optimized QCA-based memory cell is remarkable. Although there are some QCA structures for a memory cell in the literature, however, QCA characteristics may be used in designing a more optimized memory cell than blindly modeling CMOS logics in QCA. In this paper, two improved structures have been proposed for a loop-based Random Access Memory (RAM) cell. In the proposed methods, the inherent capabilities of QCA, such as the programmability of majority gate and the clocking mechanism have been considered. The first proposed method enjoys smaller number of cells and the wasted area has been reduced compared to traditional loop-based RAM cell. For the second proposed method, the memory access time has been duplicated in presence of smaller number of cells. Irregular placement of QCA cells in a QCA layout makes its realization troublesome. So, we have proposed alternative versions of the proposed methods that exploit regularity of clock zones in design and have compared them to each other. QCA designer has been employed for simulation of the proposed designs and proving their validity.     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

An efficient design of CORDIC in Quantum-dot cellular automata technology

Power dissipation of future-integrated systems, consisting of a numberless of devices, is a challenge that cannot be easily solved by classical technologies. Quantum-dot Cellular Automata (QCA) is a Field-Coupled Nanotechnology (FCN) and a potential alternative to traditional CMOS technologies. It offers various features like extremely low-power dissipation, very high operating frequency and nanoscale feature size. This study presents a novel design of CORDIC circuit based on QCA technology. The proposed circuit is based on several proposed QCA sub-modules as adder and Flip-Flop. To design and verify the proposed architecture, QCADesigner tool is employed and power consumption is estimated using QCAPro software. The proposed QCA CORDIC achieves about 69% reduction in power and area compared to previous existing designs. The outcome of this work can open up a new window of opportunity for the design of the CORDIC module and can be used in low-power signal and image processing systems.     

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata

Quantum-dot cellular automata is one of the candidate technologies used in Nano scale computer design and a promising replacement for conventional CMOS circuits in the near future. Since memory is one of the significant components of any digital system, designing a high speed and well-optimized QCA random access memory (RAM) is a remarkable subject. In this paper, a new robust five-input majority gate is first presented, which is appropriate for implementation of simple and efficient QCA circuits in single layer. By employing this structure, a novel RAM cell architecture with set and reset ability is proposed. This architecture has a simple and robust structure that helps achieving minimal area, as well as reduction in hardware requirements and clocking zone numbers. Functional correctness of the presented structures is proved by using QCADesigner tool. Simulation results confirm efficiency and usefulness of the proposed architectures vis-à-vis state-of-the-art.     

Analysis of missing and additional cell defects in sequential quantum-dot cellular automata

The defect characterization of sequential devices and circuits, implemented by molecular quantum-dot cellular automata (QCA), is analyzed in this paper. A RS-type flip–flop is first introduced; this flip–flop takes into account the timing issues associated with the adiabatic switching of this technology and its requirements. It is then shown that a D-type flip–flop can be constructed with an embedded QCA wire which extends over multiple clocking zones. The logic-level characterization of both flip–flop devices is provided. A single additional and missing cell defect model is assumed for molecular implementation. For sequential circuits, defect characterization is pursued. It is shown that defects affect the functionality of basic QCA devices, resulting mostly in unwanted inversion and majority voter acting as a wire at logic level. In this paper, it is shown that a device-level characterization of the defects and faults can be consistently extended to a circuit-level analysis.     

A class of two-dimensional cellular automata and their applications in random pattern testing

A basic framework to characterize the behavior of two-dimensional (2-D) cellular automata (CA) has been proposed. The performance of the regular structure of the 2-D CA has been evaluated for pseudo-random pattern generation. The potential increase in the local neighborhood structure for 2-D CA has led to better randomness of the generated patterns as compared to LFSR and 1-D CA. The quality of the random patterns generated with 2-D CA based built-in-self-test (BIST) structure has been evaluated by comparing the fault coverage on several benchmark circuits. Also a method of synthesizing 2-D CAs to generate patterns of specified length has been reported. The patterns generated can serve as a very good source of random two-dimensional sequences and also variable length parallel pattern generation having virtually nil correlation among the bit patterns.     

The application of single-layer graphene modified with solution-processed TiOx and PEDOT:PSS as a transparent conductive anode in organic light-emitting diodes

There are many challenges for a direct application of graphene as the electrodes in organic electronics due to its hydrophobic surfaces, low work function (WF) and poor conductance. The authors demonstrate a modified single-layer graphene (SLG) as the anode in organic light-emitting diodes (OLEDs). The SLG, doped with the solution-processed titanium suboxide (TiO_x) and poly(3,4-ethylenedio-xythiophene)/poly(styrene sulfonic acid) (PEDOT:PSS), exhibits excellent optoelectronic characteristics with reduced sheet resistance (R_sq), increased work function, as well as over 92% transmittance in the visible region. It is notable that the R_sq of graphene decreased by ∼86% from 628 Ω/sq to 86 Ω/sq and the WF of graphene increased about 0.82 eV from 4.30 eV to 5.12 eV after a modification by using the TiO_x–PEDOT:PSS double interlayers. In addition, the existence of additional TiO_x and PEDOT:PSS layers offers a good coverage to the PMMA residuals on SLG, which are often introduced during graphene transfer processes. As a result, the electrical shorting due to the PMMA residues in the device can be effectively suppressed. By using the modified SLG as a bottom anode in OLEDs, the device exhibited comparable current efficiency and power efficiency to those of the ITO based reference OLEDs. The approach demonstrated in this work could potentially provide a viable way to fabricate highly efficient and flexible OLEDs based on graphene anode.