Pentacene thin-film transistors with sol-gel derived amorphous Ba0.6Sr0.4TiO3 gate dielectric

An amorphous Ba_0.6Sr_0.4TiO₃ (BST) film with the thickness of 200 nm was deposited on indium-tin-oxide (ITO)-coated glass substrate through sol-gel route and post-annealing at 500 °C. The dielectric constant of the BST film was determined to be 20.6 at 100 kHz by measuring the Ag/BST/ITO parallel plate capacitor, and no dielectric tunability was observed with the bias voltage varying from −5 to 5 V. The BST film shows a dense and uniform microstructure as well as a smooth surface with the root-mean-square (RMS) roughness of about 1.4 nm. The leakage current density was found to be 3.5 × 10⁻⁸ A/cm² at an applied voltage of −5 V. The transmittance of the BST/ITO/glass structure is more than 70% in the visible region. Pentacene based transistor using the as-prepared BST film as gate insulator exhibits a low threshold voltage of −1.3 V, the saturation field-effect mobility of 0.68 cm²/Vs, and the current on/off ratio of 3.6 × 10⁵. The results indicate that the sol-gel derived BST film is a promising high-k gate dielectric for large-area transparent organic transistor arrays on glass substrate.     

Analysis of interface trap density of metal-oxide-semiconductor devices with Pr2O3 gate dielectric using conductance method

In this study, the interface trap density of metal-oxide-semiconductor (MOS) devices with Pr₂O₃ gate dielectric deposited on Si is determined by using a conductance method. In order to determine the exact value of the interface trap density, the series resistance is estimated directly from the impedance spectra of the MOS devices. Subsequently, the dispersion characteristics are numerically analyzed on the basis of a statistical model. Lastly, the process-dependent interface trap density of Pr₂O₃ is evaluated. It is concluded that high-pressure annealing and a superior quality interfacial SiO₂ layer are of crucial importance for achieving a sufficiently low interface trap density.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

Electroluminescence from Au/Si/SiO2/p-Si structure

Si/SiO₂ films have been grown using the two-target alternation magnetron sputtering technique. The thickness of the SiO₂ layer in all the films was 8 nm and that of the Si layer in five types of the films ranged from 4 to 20 nm in steps of 4 nm. Visible electroluminescence (EL) has been observed from the Au/Si/SiO₂/p-Si structures at a forward bias of 5 V or larger. A broad band with one peak 650–660 nm appears in all the EL spectra of the structures. The effects of the thickness of the Si layer in the Si/SiO₂ films and of input electrical power on the EL spectra are studied systematically.     

Fabrication of Ge-MOS capacitors with high quality interface by ultra-thin SiO2/GeO2 bi-layer passivation combined with the subsequent SiO2-depositions using magnetron sputtering

Ge-MOS capacitors were fabricated by a novel method of ultra-thin SiO₂/GeO₂ bi-layer passivation (BLP) for Ge surface combined with the subsequent SiO₂-depositions using magnetron sputtering. For the Ge-MOS capacitors fabricated by BLP with O₂, to decrease oxygen content in the subsequent SiO₂ deposition is helpful for improving interface quality. By optimizing process parameters of the Ge surface thermal cleaning, the BLP, and the subsequent SiO₂ deposition, interface states density of 4 × 10¹¹ cm⁻² eV⁻¹ at around mid-gap was achieved, which is approximately three times smaller than that of non-passavited Ge-MOS capacitors. On the contrary, for the Ge-MOS capacitors fabricated by BLP without O₂, interface quality could be improved by an increase in oxygen contents during the subsequent SiO₂ deposition, but the interface quality was worse compared with BLP with O₂.     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

Comparative study of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with Al2O3 and HfO2 gate oxide

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al₂O₃ gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO₂ gate oxide. The capacitance (C)-voltage (V) curve of the Al₂O₃/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C-V curve of the HfO₂/GaN diodes, indicating better quality of the Al₂O₃/GaN interface. The saturation of drain current in the I_D-V_GS relation of the Al₂O₃ AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO₂ AlGaN/GaN MOSHFETs. The gate leakage current of the Al₂O₃ MOSHFET was five to eight orders of magnitude smaller than that of the HfO₂ MOSHFETs.     

Investigation of Ta2O5/SiO2/4H-SiC MIS capacitors

Tantalum pentoxide (Ta₂O₅) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta₂O₅ of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta₂O₅. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta₂O₅ and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta₂O₅ at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta₂O₅/SiO₂/4H-SiC capacitors.     

Materials and interfaces issues in pentacene/PTCDI-C8 ambipolar organic field-effect transistors with solution-based gelatin dielectric

Gelatin is a natural protein, which works well as the gate dielectric for pentacene/N,N-dioctyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C₈) ambipolar organic field-effect transistors (OFETs) in air ambient and in vacuum. An aqueous solution process was used to form the gelatin gate dielectric film on poly(ethylene terephthalate) (PET) by spin-coating and subsequent casting. Pentacene morphology and interface roughness are two major factors affecting the electron and hole field-effect mobility (μ_FE) values of pentacene/PTCDI-C₈ ambipolar OFETs in vacuum and in air ambient. In contrast, water absorption in gelatin has higher contribution to the electron and hole μ_FE values in air ambient. The ambipolar performance of pentacene/PTCDI-C₈ ambipolar OFETs depends on their layer sequence. For example, when PTCDI-C₈ is deposited onto pentacene, i.e. in the structure of PTCDI-C₈/pentacene, unbalanced ambipolar characteristics appear. In contrast, better ambipolar performance occurs in the structure of pentacene/PTCDI-C₈. The optimum ambipolar characteristics with electron μ_FE of 0.85 cm² V⁻¹ s⁻¹ and hole μ_FE of 0.95 cm² V⁻¹ s⁻¹ occurs at the condition of pentacene (40 nm)/PTCDI-C₈ (40 nm). Surprisingly, water absorption plays a crucial role in ambipolar performance. The device performance changes tremendously in pentacene/PTCDI-C₈ ambipolar OFETs due to the removal of water out of gelatin in vacuum. The optimum ambipolar characteristics with electron μ_FE of 0.008 cm² V⁻¹ s⁻¹ and hole μ_FE of 0.007 cm² V⁻¹ s⁻¹ occurs at the condition of pentacene (65 nm)/PTCDI-C₈ (40 nm). The roles of layer sequence, relative layer thickness, and water absorption are proposed to explain the ambipolar performance.     

基于SiO2溶胶的稳定性的Cu/SiO2催化体系在化学机械抛光中的应用研究

There is a lot ofhydroxyl on the surface ofnano SiO2 sol used as an abrasive in the chemical mechanical planarization （CMP） process, and the chemical reaction activity of the hydroxyl is very strong due to the nano effect. In addition to providing a mechanical polishing effect, SiO2 sol is also directly involved in the chemical reaction. The stability of SiO2 sol was characterized through particle size distribution, zeta potential, viscosity, surface charge and other parameters in order to ensure that the chemical reaction rate in the CMP process, and the surface state of the copper film after CMP was not affected by the SiO2 sol. Polarization curves and corrosion potential of different concentrations of SiO2 sol showed that trace SiO2 sol can effectively weaken the passivation film thickness. In other words, SiO2 sol accelerated the decomposition rate of passive film. It was confirmed that the SiO2 sol as reactant had been involved in the CMP process of copper film as reactant by the effect of trace SiO2 sol on the removal rate of copper film in the CMP process under different conditions. In the CMP process, a small amount of SiO2 sol can drastically alter the chemical reaction rate of the copper film, therefore, the possibility that Cu/SiO2 as a catalytic system catalytically accelerated the chemical reaction in the CMP process was proposed. According to the van＇t Hoff isotherm formula and the characteristics of a catalyst which only changes the chemical reaction rate without changing the total reaction standard Gibbs free energy, factors affecting the Cu/SiO2 catalytic reaction were derived from the decomposition rate of Cu （OH）2 and the pH value of the system, and then it was concluded that the CuSiO3 as intermediates of Cu/SiO2 catalytic reaction accelerated the chemical reaction rate in the CMP process. It was confirmed that the Cu/SiO2 catalytic system generated the intermediate of the catalytic reaction （CuSiO3） in the CMP process through the removal rate of copper film, infrared spectrum and AFM diagrams in different pH conditions. FinalLy it is concluded that the SiO2 sol used in the experiment possesses stable performance; in the CMP process it is directly involved in the chemical reaction by creating the intermediate of the catalytic reaction （CuSiO3） whose yield is proportional to the pH value, which accelerates the removal of copper film.     

Effect of RuO2 electrode on laser-MBE prepared HfO2 gate dielectrics

In this paper, we report our recent study of the effect of RuO₂ as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO₂, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO₂ for pMOS devices. Structural, dielectric and electric properties were investigated. RuO₂/HfO₂/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm⁻¹). Compared to the SiO₂ dielectric with the same EOT value, RuO₂/HfO₂/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO₂ top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 10¹² cm⁻². All the results above indicate that RuO₂ is a promising alternative gate electrode for LMBE grown HfO₂ gate dielectrics.     

Fabrication and electrical characteristics of ultrathin (HfO2)x(SiO2)1−x films by surface sol-gel method and reaction-anneal treatment

Hafnium oxide (HfO₂) films were deposited on Si substrates with a pre-grown oxide layer using hafnium chloride (HfCl₄) source by surface sol-gel process, then ultrathin (HfO₂)_x(SiO₂)_1−x films were fabricated due to the reaction of SiO₂ layer with HfO₂ under the appropriate reaction-anneal treatment. The observation of high-resolution transmission electron microscopy indicates that the ultrathin films show amorphous nature. X-ray photoelectron spectroscopy analyses reveal that surface sol-gel derived ultrathin films are Hf-Si-O alloy instead of HfO₂ and pre-grown SiO₂ layer, and the composition was Hf_0.52Si_0.48O₂ under 500 °C reaction-anneal. The lowest equivalent oxide thickness (EOT) value of 0.9 nm of film annealed at 500 °C has been obtained with small flatband voltage of −0.31 V. The experimental results indicate that a simple and feasible solution route to fabricate (HfO₂)_x(SiO₂)_1−x composite films has been developed by means of combination of surface sol-gel and reaction-anneal treatment.     

氧化硅RIE刻蚀工艺研究

利用反应等离子刻蚀技术对SiO2进行干法刻蚀,研究了不同刻蚀条件对刻蚀速率、刻蚀选择比、刻蚀面粗糙度、刻蚀均匀性等的影响。分析得出了刻蚀侧壁角度与刻蚀选择比以及抗蚀掩模自身的侧壁角度之间存在的数学关系,这为如何获得垂直的刻蚀侧壁提供了参考。     

氧化硅RIE刻蚀工艺研究

利用反应等离子刻蚀技术对SiO₂进行干法刻蚀, 研究了不同刻蚀条件对刻蚀速率、刻蚀选择比、刻蚀面粗糙度、刻蚀均匀性等的影响。分析得出了刻蚀侧壁角度与刻蚀选择比以及抗蚀掩模自身的侧壁角度之间存在的数学关系, 这为如何获得垂直的刻蚀侧壁提供了参考。     

二氧化硅纳米花的制备及发光特性研究

采用磁控溅射和化学气相沉积技术制备出二氧化硅纳米花。利用扫描电子显微镜(SEM),X射线光电子能谱(XPS)和傅里叶红外吸收谱(FTIR)对上述纳米结构进行结构表征。用荧光光谱仪(PL)对其光致发光特性进行了研究。结果表明在激发波长为325nm时,在394nm处出现一个发光峰,表现出良好的发光特性。     

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.     

SiO2/Si上石墨烯薄膜的化学气相沉积法制备及其性能表征

以铜为催化剂,采用聚甲基丙烯酸甲酯(PMMA)和甲烷为碳源的化学气相沉积两步法,在SiO₂/Si衬底上制备了石墨烯薄膜。利用拉曼光谱分析了薄膜的层数和质量,利用光学显微镜(OM)和扫描电子显微镜(SEM)分析了薄膜的尺寸与表面形貌。实验探究了生长时间、氢气流量和气体总压强等工艺参数对石墨烯薄膜层数和质量的影响,最终在优化条件下制得10μm级质量较高的多层石墨烯薄膜。     

Effect of H2O evolving from TEOS based SiO2 film on the EEPROM cell characteristic

In this paper, we investigate the effect of water (H₂O) molecules evolving from silicon dioxide (SiO₂) film deposited by low pressure chemical vapor deposition (LPCVD) at 670 °C on the transistor characteristic of an electrically erasable programmable read only memory (EEPROM) cell. Fourier Transform Infra red (FT-IR) analysis reveals that H₂O is captured during film deposition and diffused to silicon surface during high thermal processing. The diffused H₂O molecules lower threshold voltage (V_t) of cell transistor and, thus, leakage current of the cell transistor is increased. In erased cell, V_t lowering is 0.25 V in which it increases leakage current of cell transistor from 1 to 100 pA. This results in the lowering of high voltage margin of a 512 Kb EEPROM from 2.8 to 2.6 V at 85 °C.     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

Charging effects in CdSe nanocrystals embedded in SiO2 matrix produced by rf magnetron sputtering

Charging effects in CdSe nanocrystals embedded in SiO₂ matrix fabricated by rf magnetron co-sputtering technique were electrically characterized by means of capacitance-voltage (C-V) combined with current-voltage (I-V). The presence of CdSe nanocrystals was demonstrated by X-ray diffraction technique. The average size of nanocrystals was found to be approximately 3 nm. The carriers transport in the CdSe/SiO₂ structure was shown to be a combination of Fowler-Nordheim tunnelling and Poole-Frenkel mechanisms. A memory effect was demonstrated and a retention time was measured.