Effect of temperature in selective buried oxide TFET in the presence of trap and its RF analysis

This work explores the temperature associated reliability issues of selective buried oxide (SELBOX) TFET. The proposed device is optimized for maximum I_ON/I_OFF ratio considering various gap positions in the buried oxide. The variation of DC parameters such as I_D‐V_GS characteristics, subthreshold swing (SS) and I_ON/I_OFF ratio for a wide range of temperature from 300 K to 500 K has been studied. The proposed SELBOX device is compared with conventional silicon‐on‐insulator device considering various RF parameters. Moreover, the dependency of RF performance of the proposed device on temperature has been examined. The variation of RF parameters such as transconductance (g_m), cut‐off frequency (f_T), gate capacitance (C_GG), intrinsic delay and transconductance frequency product (TFP) with temperature has also been studied. The linearity of the device has been explored by analyzing the influence of temperature variation on 1‐dB compression point. Further, temperature dependency in the presence of quantum correction (QC) model has been analyzed.     

Impact of sidewall spacer on n-InGaAs devices and hybrid InGaAs/Si CMOS amplifiers in deca-nanometer regime

In this paper, we report, for the first time, the influence of the sidewall spacers (SWS) on the analog performance of InGaAs nMOSFETs at channel lengths of 32 and 22 nm. The study is further extended to the circuit level in which the impact of spacer layer on hybrid CMOSFETs comprising InGaAs nMOSFETs and Si pMOSFETs is thoroughly investigated in analog domain. Using extensive numerical analysis we study the impact of SWS layers on various device parameters e.g., transconductance (g_m), transconductance efficiency (g_m/I_D), output conductance (g_d) and intrinsic gain (g_m/g_d) related to analog applications. Then, the hybrid CMOS current source load amplifier is studied in terms of voltage gain, total capacitance (C_Total) and gain bandwidth product (GBW). The simulation scheme is validated with reported experimental data in the literature. Our findings reveal that all the parameters at the device level, except g_d exhibit improved performance for higher value of spacer k. On the contrary, g_d decreases with reduced k-value and becomes weakly sensitive to the variation in spacer length (L_sp), for the InGaAs nMOS device having channel lengths (L_g) of 22 and 32 nm. At the circuit level, for the hybrid CMOS amplifier, we found that the dc-gain and C_Total exhibit larger value for higher value of L_sp, while GBW shows higher value for reduced L_sp. Our investigation suggests that improved analog performance of InGaAs nMOSFETs with suitable SWS engineering may be achieved at more advanced technology nodes.

     

Analysis of interface states of metal–insulator–semiconductor photodiode with n-type silicon by conductance technique

A metal–insulator–semiconductor photodiode (MIS-PD) as active layer with n-type silicon as interdigitated Schottky electrodes has been fabricated. The current–voltage characteristics, density of interface states and photovoltaic properties of the MIS-PD diode have been investigated. The diode has a metal–insulator–semiconductor configuration with ideality factor higher than unity. The electronic parameters (ideality factor, series resistance and barrier height) of the diode were found to be 1.94, 2.23 × 10⁴ Ω and 0.74, respectively. At voltages between 0.13 and 0.50 V, the charge transport mechanism of the diode is controlled by space charge-limited current mechanism. The interface state density of the diode was found to vary from 5.54 × 10¹² to 5.67 × 10¹² eV⁻¹ cm⁻² with bias voltage. The Au/SiO₂/n-Si/Al device shows a photovoltaic behavior with a maximum open circuit voltage V_oc of 97.7 mV and short-circuit current I_sc of 17.4 μA under lower illumination intensities. The obtained electronic parameters confirm that the Au/SiO₂/n-Si/Al diode is a MIS type photodiode.     

Gain–bandwidth limitations of microwave transistor

This work enables one to obtain the potential gain (G_T) characteristics with the associated source (Z_S) and load (Z_L) termination functions, depending upon the input mismatching (V_i), noise (F), and the device operation parameters, which are the configuration type (CT), bias conditions (V_DS, I_DS), and operation frequency (f). All these functions can straightforwardly provide the following main properties of the device for use in the design of microwave amplifiers with optimum performance: the extremum gain functions (G_{T max}, G_{T min}) and their associated Z_S, Z_L terminations for the V_i and F couple and the CT, V_DS, I_DS, and f operation parameters of the device point by point; all the compatible performance (F, voltage–standing wave ratio V_i, G_T) triplets within the physical limits of the device, which are F ≥ F_min, V_i ≥ 1, G_{T min} ≤ G_T ≤ G_{T max}, together with their Z_S, Z_L termination functions; and the potential operation frequency bandwidth for a selected performance (F, V_i, G_T) triplet. The selected performance triplet and termination functions can be realized together with their potential operation bandwidth using the novel amplifier design techniques. Many examples are presented for the potential gain characteristics of the chosen low‐noise or ordinary types of transistor. © 2002 Wiley Periodicals, Inc. Int J RF and Microwave CAE 12, 483–495, 2002. Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mmce.10049     

A LTPS-TFT pixel circuit for active matrix organic light emitting diode based on improved current mirror

In this paper, a voltage-driving and current compensation method for active matrix organic light emitting diode (AMOLED) displays is proposed. An improved current mirror is introduced into the pixel circuit to overcome the channel length modulation effect of TFTs. The SPICE simulation results show that the proposed pixel circuit not only effectively compensates for non-idealities related with deviations of μ and V_T in TFTs, the OLED degradation, but also offers a less setting time and guarantees a good liner relationship between V_DATA and I_OLED.     

High-K Spacer Dual-Metal Gate Stack Underlap Junctionless Gate All Around (HK-DMGS-JGAA) MOSFET for high frequency applications

High-K Spacer based Dual-Metal Gate Stack Junctionless Gate All Around (HK-DMGS-JGAA) MOSFET has been proposed and analyzed in this paper for high frequency analog ad RF applications. It has been done by comparing it with the existing Junctionless devices in particular, Junctionless-Gate All Around, Junctionless Gate All Around Underlap and Dual-Metal Junctionless Gate All Around Underlap MOSFET. It is so found that HK-DMGS-JGAA MOSFET shows higher I_ds, g_m, g_d and f_T over existing Junctionless device architectures making it a suitable device for high frequency analog applications. It has also been established that HK-DMGS-JGAA MOSFET has better I_ON/I_OFF ratio, Subthreshold Slope (SS) most close to the ideal values, lower Channel Resistance, R_ch, higher Early Voltage (V_EA), higher Frequency Transconductance Product, superior Transconductance Generation Factor, Maximum gains in terms of current gain, Maximum Transducer Power Gain and Unilateral Power Gain, superior noise performance in terms of the Noise Conductivity and Noise Figure. All these improved figure of merits warrant HK-DMGS-JGAA MOSFET as the best suited device design for various analog and digital applications along with high frequency applications.

     

Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications

This paper presents a mathematical modeling insight for the novel heterogate dielectric-dual material gate-GAA TFET (HD-DMG-GAA-TFET) and validating the results with TCAD simulation. By using the appropriate boundary conditions and continuity equations, the Poisson’s equation is solved to obtain the potential profile. The developed model is used to study the analog performance parameters such as subthreshold swing (SS), threshold voltage (V_th), transconductance (g_m), drain conductance (g_d), device efficiency (g_m/I_ds), intrinsic gain (g_m/g_d), channel resistance (R_ch) and output resistance (R_o). Further, to optimize the effect of metal work function on analog performance, three different combinations of DMG configurations has been studied. The results demonstrated that for a difference of 0.4 eV, the analog performance of the device is optimized. Low off current and high value of on current resulting into a higher I_ON/I_OFF ratio has been obtained, which is appropriate for sub-nanometre devices and low standby power applications. The analytical results obtained from the proposed model shows good agreement with the simulated results obtained with the ATLAS device simulator.

     

Assessment of analog RF performance for insulated shallow extension (ISE) cylindrical surrounding gate (CSG) MOSFET incorporating gate stack

In this paper, insulated shallow extension cylindrical surrounding gate (ISE-CSG) MOSFET with high-k gate stack has been proposed and extensively investigated. The performance of high-k ISE-CSG MOSFET has been compared with cylindrical surrounding gate MOSFET. ISE-CSG with high-k gate stack has number of desirable features at 30 nm regimes. The results reveal that ISE-CSG MOSFET with gate stack is more immune to short channel effects because of improved carrier transportation capability. It has been observed that high-k ISE-CSG MOSFET shows improved figure of merits as drive current (I_ON), I_ON/I_OFF ratio, transconductance (g_m), cutoff frequency f_T, transconductance generation factor, intrinsic gain (A_v), transconductance frequency product, gain transconductance frequency product and gain frequency product. ISE-CSG with high-k gives better control over the depletion region and therefore it is a suitable device for high speed, high frequency and analog/RF circuit applications.

     

A design approach of higher oscillation VCO made of CS amplifier with varying active load

This article proposes a design approach of common source (CS) amplifier based Voltage Controlled Oscillator (VCO) to derive higher oscillation frequency. The working feature is such that, the active load of CS amplifier is varied to modulate the flow of current based on a bias circuit steered by an external controlled voltage (V_ctrl), which controls the delay of each stage and thereby regulates the oscillation frequency. The circuit is designed and analyzed on Cadence Virtuoso platform at a supply voltage of 1.2 V for 90 nm CMOS to read a device footprint of 0.105 mm², which offers a power burn and frequency of 2.092 mW and 9.21 GHz respectively with a phase noise and output noise of − 137.9 dBc/Hz and − 168.40 dB at 1 MHz offset frequency. To justify the reliability of the circuit we have conducted worst case analysis by considering effect of power delivery network (PDN) and corner variation along with 500 runs of Monte Carlo. The design is also introduced under 28 nm UMC to validate its scalability with technology trends.

     

Design of low power,high speed 4 bit binary to Gray converter with 8 × 4 barrel shifter using nano dimensional MOS transistor for arithmetical,logical and telecommunication circuit and system application

In this work the design of 4 bit binary to Gray code converter circuit with 8 × 4 barrel shifter has been carried out. The circuit has been designed using metal oxide semiconductor (MOS) transistor. The verification of the functionality of the circuits has been performed using Tanner-SPICE software. Power consumption and speed are the major design metrics for very large scale integrated circuit. In this work the average power consumption and gate delay analysis of 4 bit binary to Gray converter with 8 × 4 barrel shifter has been carried out using nano dimensional MOS transistor having channel length of 150 nm. Power consumption, delay analysis has been carried out for different set of supply voltage. It has been observed that power consumption of the 4 bit binary to Gray converter with 8 × 4 barrel shifter has been reduced by reducing the power supply voltage V_DD. The power consumption and delay offers by the circuit is very less. At 1 V V_DD, power consumption and delay are 0.15 μW and 52.7 ps respectively. Therefore the circuit is suited for low power and high speed application in the area of arithmetical, logical and telecommunication.

     

DEPARTMENT OF SCIENTIFIC AND INDUSTRIAL RESEARCH: HUMAN SCIENCES COMMITTEE

Maximal power output during short term constant velocity cycling and vertical jumping from a force platform has been studied in five healthy young male subjects. From the measurements on the force platform the peak (instantaneous) power output (P), net impulse (I_N ), force (F₁ ). velocity of take-off(V_T ) and height of jump(h) were calculated. The corresponding values for power (H), force (F) and velocity (V) on the bicycle were obtained from analysis of the force-velocity relationship.

The results (mean ± S.D.) showed that on the force platform F₁ P, I_N, V_T and h were 1073± 167N, 2205±310W, 154±17Ns, 2·48+0·15ms^?1 and 31 +4cm. h was positively associated with both I_N (r= +0·77) and P (r = 0·67). The mean maximal power output for cycling was 854W(39%) greater than jumping and was achieved at a 271N (25%) increase in F and a reduction in V. Nevertheless they were closely related.

Platform P(W) = 717·6 + 0·483 bicycle H(W) r= +0·74

A comparison of linear and curvilinear (hyperbolic) analysis of the F/V bicycle data showed that the latter did not reduce the variance of observations and was not, therefore, statistically justifiable (Wilkie 1950). The mean intra-subject variations of P and H were 6·6%± 1·8 and 40%+1·2. The relative values of F and V at H were both found to be approximately 50% of their respective maximal values.

It was concluded that short term power output can be measured simply and accurately in man during the performance of two activities. Rotational movement of the legs as in cycling produces higher values of peak power output then vertically lifting body weight. For the achievement of peak power output in cycling, relative force and speed of movement must both correspond to approximately half of their respective maximal values.     

SteamTables: An approach of multiple variable sets

Using the IAPWS-95 formulation, an ActiveX component SteamTablesIIE in Visual Basic 6.0 is developed to calculate thermodynamic properties of pure water as a function of two independent intensive variables: (1) temperature (T) or pressure (P) and (2) T, P, volume (V), internal energy (U), enthalpy (H), entropy (S) or Gibbs free energy (G). The second variable cannot be the same as variable 1. Additionally, it calculates the properties along the separation boundaries (i.e., sublimation, saturation, critical isochor, ice I melting, ice III to ice IIV melting and minimum volume curves) considering the input parameter as T or P for the variable 1.SteamTablesIIE is an extension of the ActiveX component SteamTables implemented earlier considering T (190 to 2000 K) and P (3.23×10^?8 to 10000 MPa) as independent variables. It takes into account the following 27 intensive properties: temperature (T), pressure (P), fraction, state, volume (V), density (Den), compressibility factor (Z₀), internal energy (U), enthalpy (H), Gibbs free energy (G), Helmholtz free energy (A), entropy (S), heat capacity at constant pressure (C_p), heat capacity at constant volume (C_v), coefficient of thermal expansion (CTE), isothermal compressibility (Z_iso), speed of sound (VelS), partial derivative of P with T at constant V (dPdT), partial derivative of T with V at constant P (dTdV), partial derivative of V with P at constant T (dVdP), Joule-Thomson coefficient (JTC), isothermal throttling coefficient (IJTC), viscosity (Vis), thermal conductivity (ThrmCond), surface tension (SurfTen), Prandtl number (PrdNum) and dielectric constant (DielCons).     

Improved Algorithms and Complexity Results for Power Domination in Graphs

The NP-complete Power Dominating Set problem is an “electric power networks variant” of the classical domination problem in graphs: Given an undirected graph G=(V,E), find a minimum-size set P?V such that all vertices in V are “observed” by the vertices in P. Herein, a vertex observes itself and all its neighbors, and if an observed vertex has all but one of its neighbors observed, then the remaining neighbor becomes observed as well. We show that Power Dominating Set can be solved by “bounded-treewidth dynamic programs.” For treewidth being upper-bounded by a constant, we achieve a linear-time algorithm. In particular, we present a simplified linear-time algorithm for Power Dominating Set in trees. Moreover, we simplify and extend several NP-completeness results, particularly showing that Power Dominating Set remains NP-complete for planar graphs, for circle graphs, and for split graphs. Specifically, our improved reductions imply that Power Dominating Set parameterized by |P| is W[2]-hard and it cannot be better approximated than Dominating Set.     

Electrical and photoelectrical characterizations of isotype GaAs15P85/GaP heterojunctions prepared by liquid phase epitaxy

The present work deals with the electrical and optoelectronic characterizations of the isotype GaAs₁₅P₈₅/GaP devices prepared by liquid phase epitaxy. The electrical properties of the fabricated junction were studied by analyzing its current–voltage (I–V) characteristics, capacitance–voltage (C–V) characteristics in the dark at different temperatures in the range of 300–450 K. The analysis of dark current–voltage (I–V) characteristics at different temperatures were presented in order to elucidate the conduction mechanism and to evaluate the important device parameters. The predominant charge transport mechanism in these devices was found to be thermionic emission in the depletion layer and over the barrier of GaAs₁₅P₈₅/GaP heterojunction at forward bias voltage. From the capacitance–voltage, measurements at high frequency (1 MHz) information can be obtained about the carrier concentration, the diffusion potential, the barrier height of GaAs₁₅P₈₅/GaP heterojunction. The current–voltage characteristics of the GaAs₁₅P₈₅/GaP heterojunction under different illumination intensities were studied. The power low dependence of the reverse current voltage is characterized by space charge limited conduction, SCLC dominated by exponential trap distribution at the higher reverse voltage region.     

Study of enhanced DC and analog/radio frequency performance of a vertical super-thin body FET by high-k gate dielectrics

This article reports the DC and analog/radio frequency (RF) response of a newly invented device called vertical super-thin body (VSTB) FET towards high-k (Si₃N₄/HfO₂) and low-k (SiO₂) gate dielectrics in conjunction with the scaling effect through a well-calibrated Sentaurus TCAD tool. At channel length (L_G) of 20 nm, compared to SiO₂, Si₃N₄ improves various DC parameters such as off-state leakage current (I_off), on-current (I_on), on-to-off current ratio (I_on/I_off ratio), subthreshold swing (SS), and drain-induced-barrier-lowering (DIBL) by 77.15%, 26.2%, one order of magnitude, 15.78%, and 36.2%, respectively. On the other hand, a higher improvement is seen in all these DC parameters for the HfO₂ gate dielectric (I_off, I_on, I_on/I_off ratio, SS, DIBL improves respectively by 91.8%, 41.57%, two orders of magnitude, 28.28%, and 62.71%). The underlying physics behind such excellent improvement is explained by the device off-state energy band diagram, electrostatic potential, and channel electron density profile for each dielectric. Further, for all the gate dielectrics considered, the device characteristics were studied for a wide range of L_G from 10 to 50 nm to reveal the scaling impact on the device performance. Irrespective of the gate dielectric material, the device exhibits excellent performance at L_G = 10 nm, which in turn indicates to the brilliant scalability of this new device. Besides, although Si₃N₄ and HfO₂ increase gate capacitance (C_gg)/gate-drain capacitance (C_gd), due to the extremely low values of C_gg/C_gd, enhanced unit gain cut-off frequency, and gain-bandwidth-product is achieved. In addition, the increased transconductance (g_m) of the device applying Si₃N₄/HfO₂ gate dielectric leads to a higher peak value of TGF, intrinsic gain, TFP, GFP, and GTFP. This study intends to expand the fundamental knowledge about such a new device as a VSTB FET and hence, aims to be utilized in the future research of this novel device.     

An external compensation method for AMOLED using the concept of ramp‐stop

In this paper, we propose an external feedback method to compensate the device variation for active‐matrix organic light‐emitting diode. The pixel data current is controlled by ramping the gate voltage and converted to the sensed voltage V_sense in real time. When V_sense is equal to a preset voltage V_data, the switching block outputs the low potential to stop the ramping. Therefore, the gate voltage is locked at the value corresponding to the target data current. This circuit is implemented with three thin‐film transistors in the active area and some functional blocks in driver integrated circuit (IC), namely, sentinel block, current‐voltage converting block, and switching block. Unlike the other usual methods of external compensation requiring double number of connections between driver IC and glass, by using the common ramping signal and a simple circuit made on glass, the proposed method can be implemented with only one pin per column.     

A New Approach to Primary Decomposition

The first purpose of this paper is to describe a new mathematical approach for the computation of an irredundant primary decomposition of a given polynomial ideal I. This presentation will be formed of three parts: a decomposition of the associated radical ideal I to an intersection of prime ideals P_i, then the determination of ideals I_iwhose radical is prime (equal to P_i), and finally, the extraction of the possible embedded components included in I_i. The second is to give an implementation of this algorithm via a new software component, called The Central Control², in which we implemented distributed algorithms performing the basic operations of algebraic geometry.     

A fine-grained data-flow analysis framework

 A fine-grained data-flow analysis framework (L, F) where the elements of the semilattice L are mappings from a set of items I to a semilattice of values V is introduced, and an algorithm is presented to solve this framework by considering the elements of I and V individually, rather than regarding the elements of L as atomic values. It is shown that a variety of useful data-flow problems fit into the fine-grained data-flow analysis framework, and can be solved in O(∣I∣×∣N∣) time. Received 20 August, 1991/ 3 June, 1996     

Cryptanalysis of an MOR cryptosystem based on a finite associative algebra基于有限结合代数的 MOR 公钥密码安全性分析

The Shor algorithm is effective for public-key cryptosystems based on an abelian group. At CRYPTO 2001, Paeng (2001) presented a MOR cryptosystem using a non-abelian group, which can be considered as a candidate scheme for post-quantum attack. This paper analyses the security of a MOR cryptosystem based on a finite associative algebra using a quantum algorithm. Specifically, let L be a finite associative algebra over a finite field F. Consider a homomorphism φ: Aut(L) → Aut(H)×Aut(I), where I is an ideal of L and H ? L/I. We compute dim Im(φ) and dim Ker(φ), and combine them by dim Aut(L) = dim Im(φ)+dim Ker(φ). We prove that Im(φ) = Stab_Comp(H,I)(μ + B²(H, I)) and Ker(φ) ? Z¹(H, I). Thus, we can obtain dim Im(φ), since the algorithm for the stabilizer is a standard algorithm among abelian hidden subgroup algorithms. In addition, Z¹(H, I) is equivalent to the solution space of the linear equation group over the Galois fields GF(p), and it is possible to obtain dim Ker(φ) by the enumeration theorem. Furthermore, we can obtain the dimension of the automorphism group Aut(L). When the map ? ∈ Aut(L), it is possible to effectively compute the cyclic group 〈?〉 and recover the private key a. Therefore, the MOR scheme is insecure when based on a finite associative algebra in quantum computation.