The design of fully differential CMOS operational amplifiers without extra common-mode feedback circuits

A new fully differential CMOS operational amplifier (op amp) without extra common-mode feedback (CMFB) circuit is proposed and analyzed. In this op amp, simple inversely connected current-mirror pairs are used as active loads. From the theoretical analysis, it is shown that the common-mode signal can be efficiently suppressed by the reduced effective common-mode resistance of the active load. The proposed op amp with 2 pF capacitance loadings has an open-loop unity-gain bandwidth of 63 MHz, a phase margin 47°, and a dc gain of 67 dB in 3.5µm p-well CMOS technology. The common-mode gain at a single output node can be as low as —38 dB without extra CMFB circuit. Experimental results have successfully confirmed the capability of the efficient common-mode rejection.This work was supported by the United Microelectronics Corporation (UMC), Republic of China, under Grant C80054.     

Rail-to-rail BiCMOS operational amplifier using input signal adapters with floating outputs

An operational amplifier with rail-to-rail input and output voltage range in 0.6 μm BiCMOS technology is presented. Two simple input signal adapters with floating outputs serving as pre-stages are introduced. They are followed by a differential amplifier. The adapters translate the input signals into a floating level within the operating region of the differential amplifier, enabling rail-to-rail operation. An inverter-based simple rail-to-rail class AB output stage has been used. With a single supply of 1.5 V, the proposed rail-to-rail operational amplifier achieves 72 dB DC open-loop gain, 2.54 MHz unity-gain frequency, 62° phase margin, 2.5 V/μs slew rate, and 147 μW power consumption.     

Low-voltage operational amplifier with rail-to-rail input and output ranges

An operational amplifier is described which can perform precision signal operations in nearly the full supply voltage range, event when this range is as low as 1.5 V totally. The untrimmed input offset voltage is typically 0.3 mV in an input common-mode (CM) voltage range which extends beyond both supply voltages for about 200 mV. The output voltage can reach each supply rail within 150 mV. A nested-loop frequency-compensation scheme yields a stable unity-gain bandwidth of 0.6 MHz while the low-frequency open-loop voltage gain is 110 dB. The op amp is integrated in a standard low-cost bipolar process and the chip measures 1.5/spl times/1.7 mm/SUP 2/.     

采用输入信号适配技术的BiCMOS运放

为了满足高性能开关电源中集成运放的应用需要,设计了一种结构简单且具有轨对轨输出的运算放大器.该运放基于0.5μm BiCMOS 工艺,采用浮动输出的输入信号适配器(ISAFO),将输入信号放大至差分输入级的工作区域,从而实现了轨对轨的运行.对所设计的运放进行了仿真分析,结果表明在工作电源电压为±0.75 V、外接100 kΩ电阻的条件下,该运放的直流开环增益达到了102 dB,单位增益-带宽为6.35 MHz,相位裕度为62.5°,而功耗仅约为150 μW.所设计的运放具有很宽的共模输入范围及较高的增益,所以特别适用于开关电源的误差放大器、过流、过压和过热保护模块中.     

Large bandwidth BiCMOS operational amplifiers for SC videoapplications

A single-ended and a fully differential broadband BiCMOS operational amplifier for switched-capacitor video applications are presented. The amplifiers feature a folded cascode gain stage with a current source as output load. For the single-ended amplifier the current mirroring is accomplished with a modified bipolar Wilson current mirror at the output of the differential pair. Symbolic expressions for the transfer functions for both amplifiers are derived. The amplifiers are integrated in an analog 1 μm BiCMOS process with an active die area of 0.72 mm² and 0.96 mm² for the single-ended and the fully differential amplifier, respectively. For both amplifiers a DC-gain of 68 dB and a unity gain frequency greater than 250 MHz was measured for a power supply voltage of 5 V     

低功耗恒定跨导轨对轨运算放大器设计技术研究

为了解决轨对轨运算放大器输入级跨导随共模输入电压变化的影响,采用实时共模电压监测技术,动态跟踪轨对轨运放输入级的跨导变化,通过对偏置电流的高精度定量补偿,从而实现了对输入级跨导的恒定性控制。基于0.18μm CMOS工艺进行了具体电路的设计实现,结果表明:在电源电压3.3 V、负载电阻100Ω、负载电容1 nF的条件下,运放增益为148 dB、相位裕度为61°、功耗为39.6μW,共模输入范围高达0~3.3 V,输入级跨导变化率仅为2.1%。     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。     

Operational amplifier with 1-V rail-to-rail multipath-driven outputstage

A bipolar operational amplifier (op amp) with a rail-to-rail multipath-driven output stage that operates at supply voltages down to 1 V is presented. The bandwidth of this output stage is as high as possible, viz, equal to that of one of the output transistors, loaded by the output capacitance. The output voltage can reach both supply rails within 100 mV and the output current is ±15 mA. The op amp is designed to be loaded by a 100-pF capacitor and the unity-gain bandwidth is 3.4 MHz at a 60° phase margin. The voltage gain is 117 dB and the CMRR is 100 dB. The frequency behavior of the multipath-driven (MPD) topology has an improved performance when compared to that of previously presented low-voltage output stages. A figure of merit F_M for low-voltage op amps has been defined as the bandwidth-power ratio     

1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage

This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output     

A rail-to-rail CMOS op amp

A CMOS op amp (operational amplifier) is reported which has a rail-to-rail voltage range at its input as well as its output. An area-efficient output stage has been used. While the entire op amp occupies only 600 mil², when used as a unity-gain buffer and with ±5-V supplies, the op amp can drive a 9-V_pp/1-kHz sine wave across a 300-Ω load with -64 dB of harmonic distortion     

基于最小电流选择的运算放大器设计

设计了一种工作电压为3V恒跨导满幅CMOS运算放大器,针对轨对轨输入级中存在的跨导不恒定和简单AB类输出级性能偏差这2个问题,提出了利用最小电流选择电路来稳定输入级的总跨导;浮动电流源控制的无截止前馈AB类输出级实现了运放的满幅输出,同时减小了交越失真。该电路通过HSpice进行仿真验证,在0～3V输入共模范围内,输入级跨导的变化小于3.3%,开环增益为93dB,单位增益带宽为8MHz,相位裕量为66°。     

A high-swing CMOS telescopic operational amplifier

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulated-cascode differential gain enhancement and a replica-tail feedback technique. A prototype of the op-amp has been built in a 0.81-μm CMOS process. Operating from a power supply of 3.3 V, it achieves a differential swing of ±2.15 V, a differential gain of 90 dB, unity-gain frequency of 90 MHz, and >50-dB CMRR. It is shown, analytically and through simulations, that the operational amplifier maintains its high CMRR even at high frequencies     

Effective parameter extraction using multiple-objective function for VLSI circuits

In this paper an input stage and an output stage are presented for application in low-voltage CMOS operational amplifiers. The input stage operates in strong inversion and has a rail-to-rail common-mode input voltage range. The transconductance (g _m ) is insensitive to the common-mode input voltage. The class AB output stage has a rail-to-rail output range. A class AB control circuit prevents any transistors in the output stage from switching off. This improves the large-signal high-frequency behavior and the step response of the amplifier. A complete two-stage Op Amp employing the proposed input and output stages was realized in a semi-custom CMOS process with minimum channel lengths of 10µm and transistor threshold voltages of approximately 0.7 V. The measured minimum supply voltage is 2.5 V. The measured input voltage range exceeds the supply rails and the output voltage reaches both rails within 130 mV. The unity-gain bandwidth of the complete Op Amp is severely limited by the long channel lengths. Simulations show that a unity-gain bandwidth of 7 MHz is feasible if 2.5µm channel lengths are used.     

低电压高增益带宽CMOS折叠式共源共栅运算放大器设计

本文基于SIMC 0．18μm CMOS工艺模型参数,设计了一种低电压高单位增益带宽CMOS折叠式共源共栅运算放大器。该电路具有相对高的单位增益带宽,并具有开关电容共模反馈电路（CMFB）稳定性好、对运放频率特性影响小的优点,Hspice仿真结果表明,在1．8V电压下,运算放大器的直流开环增益为62．1dB,单位增益带宽达到920MHz。     

一种适合VLSI库的Rail-to-Rail运算放大器

介绍了一种适于 VLSI库单元的轨到轨 (Rail-to-Rail)运算放大器。低电压、低功耗、输入输出动态幅度达到 Rail-to-Rail的运放模块是研究的核心。文章分析了该运放模块的输入、输出级 ,并分析了 cascodedMiller频率补偿技术。芯片采用新加坡特许半导体制造公司 0 .6μm N阱 CMOS工艺 ,芯片面积 0 .0 2 4mm2 。测试结果表明 :该运放模块在 3 V工作电压下直流增益 90 d B,共模输入范围 -0 .4～ 4V,输出动态范围 0～ 2 .9V,单位增益带宽 7MHz,相位裕量 70°,静态功耗仅有 0 .3 m W,特别适合作为 VLSI的库单元     

A BiCMOS wideband operational amplifier with 900 MHz gain-bandwidth and 90 dB DC gain

A fully differential operational amplifier has been designed and fabricated for a novel high resolution and high frequency analog-to-digital converter(>12-bit). The amplifier mainly consists of folded cascode structure with current source as output loads and common-mode feedback circuits. The technique of feedforward compensation is used in order to improve the settling time and gain bandwidth (GBW) of this amplifier. This amplifier is integrated in 0.8 mm BiCMOS process with an active die area of 0.1 mm². The DC gain of this amplifier is 90 dB. The GBW and phase margin of this amplifier is 900 MHz and 47°, respectively. The power dissipation is minimized by using BiCMOS technology and is about 25 mW for 2 pF load capacitance. This level of performance is competitive with CMOS and BiCMOS operational amplifier circuits previously reported by nearly two orders of magnitude.Ecole Polytechnique of the University of Montreal     

High-speed GaAs operational amplifier

An operational amplifier has been designed and fabricated using GaAs MESFETs. This amplifier is a general-purpose monolithic GaAs op amp designed as as a stand-alone component. The amplifier has a differential input, an open-loop gain in excess of 60 dB, and is internally compensated. The high open-loop gain (60 dB at 100 kHz) was achieved by using gain stages with positive feedback. The op amp incorporates a current-mirror level-shifting stage which allows the op amp to operate over a wide power-supply range (/spl plusmn/5-9 V). Previous designs have diodes to achieve level shifting, a practice that precludes operation over a wide supply range. This op amp is a true analog to its silicon counterparts, but it has a higher gain-bandwidth product.     

一种恒跨导轨对轨CMOS运算放大器的设计

设计了一种新颖的恒跨导轨对轨CMOS运算放大器结构。输入级采用轨对轨的结构,在输入级采用4个虚拟差分对管来对输入差分对的电流进行限制,使运放的输入级跨导在工作范围内保持恒定。输出级采用前馈式AB类输出结构,以使输出达到全摆幅。仿真结果显示,在5 V电源电压和带有10 pF电容与10 kΩ电阻并联的负载下,该运放在共模输入范围内实现了恒跨导,在整个共模输入范围内跨导变化率仅为3%,输出摆幅也达到了轨对轨全摆幅,运放的开环增益为108.5 dB,增益带宽积为26.7 MHz,相位裕度为76.3°。     

High-gain gaas mesfet op amp

A gain enhancement technique for GaAs MESFET op amps is presented. It uses positive feedback to cancel the output conductance between the driver and active load transistors in a common-source amplifier configuration. An op amp using this technique was implemented in a 1-µm non-self-aligned GaAs MESFET process. The op amp exhibited a dc gain of 60 dB and a unity-gain frequency of 840 MHz.Please address all correspondence to C.A.T. Salama.     

On the performance of the differential cascode amplifier

Analysis is made of the differential cascode amplifier stage, an amplifier made of a differential common-emitter input pair driving a differential common-base output pair referenced to the emitter potential of the input pair. The analysis shows the differential cascode amplifier to have one or more orders of magnitude increase in common-mode input resistance and common-mode rejection ratio compared to that of a conventional differential pair. Consideration is also given to the use of junction field-effect transistors for either pair in the differential cascode stage. The frequency response of the stage is studied, and a potentially troublesome common-mode complex pole pair is identified as the one disadvantage of the differential cascode circuit.